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參數(shù)資料
| 型號： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 2/95頁 |
| 文件大?。?/td> | 1399K |
| 代理商： | AM79Q062JC |
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10
Am79Q06/061/062/063 Data Sheet
CHCLK
Output
Chopper Clock. This output provides a 256 kHz or a 292.57 kHz, 50% duty cycle, TTL-compatible
clock for use by up to four SLICs with built-in switching regulators. The CHCLK frequency is syn-
chronous to MCLK/DCL (MCLK in PCM mode, DCL in GCI mode), but the phase relationship to
MCLK/DCL is random. The chopper clock is not available in all package types.
CS/PG
Input
Chip Select/PCM-GCI. The CS/PG input along with the DCLK/S0 input are used to determine the
operating state of the programmable PCM/GCI interface. On power up, the QSLAC device will
initialize to GCI mode if CS/PG is low and there is no toggling (no high to low or low to high tran-
sitions) of the DCLK/S0 input. The device will initialize to the PCM/MPI mode if either CS is high
or DCLK is toggling.
Once the device is in PCM/MPI mode, it is ready to receive commands through its serial interface
pins, DIO and DCLK. Once a valid command has been sent through the MPI serial interface, GCI
mode cannot be entered unless a hardware reset is asserted or power is removed from the part.
If a valid command has not been sent since the last hardware reset or power up, then GCI mode
can be re-entered (after a delay of one PCM frame) by holding CS/PG low and keeping DCLK
static. While the part is in GCI mode, then CS/PG going high or DCLK toggling will immediately
place the device in PCM/MPI mode.
In the PCM/MPI mode, the Chip Select input (active Low) enables the device so that control data
can be written to or read from the part. The channels selected for the write or read operation are
enabled by writing 1s to the appropriate bits in the Channel Enable Register of the QSLAC device
prior to the command. See EC1, EC2, EC3, and EC4 of the Channel Enable Register and Com-
mand 14 for more information. If Chip Select is held Low for 16 rising edges of DCLK, a hardware
reset is executed when Chip Select returns High.
DCLK/S0
Input
Data Clock. In addition to providing both a data clock input and an S0 GCI address input, DCLK/
S0 acts in conjunction with CS/PG to determine the operational mode of the system interface,
PCM/MPI or GCI. See CS/PG for details.
In the PCM/MPI mode, the Data Clock input shifts data into and out of the microprocessor inter-
face of the QSLAC device. The maximum clock rate is 4.096 MHz and the minimum clock rate is
10 kHz.
Input
Select Bit 0. In GCI mode, S0 is one of two inputs (S0, S1) that is decoded to determine on which
GCI channels the QSLAC transmit and receives data.
DIO/S1
Input
Data Input Output. In the PCM/MPI mode, control data is serially written into and read out of the
QSLAC device via the DIO pin, most significant bit first. The Data Clock determines the data rate.
DIO is high impedance except when data is being transmitted from the QSLAC device.
Input
Select Bit 1. In GCI mode, S1 is the second of two inputs (S0, S1) that is decoded to determine
on which GCI channels the QSLAC transmits and receives data.
DRA,
DRB/DD
Inputs
PCM Data Receive (A/B). In the PCM/MPI mode, the PCM data for Channels 1, 2, 3, and 4 is
serially received on either the DRA or DRB port during user-programmed time slots. Data is al-
ways received with the most significant bit first. For compressed signals, 1 byte of data for each
channel is received every 125 s at the PCLK rate. In the Linear mode, 2 consecutive bytes of
data for each channel are received every 125 s at the PCLK rate. DRB is not available on all
package types.
Input
GCI Data Downstream. In GCI mode, the B1, B2, Monitor and SC channel data is serially re-
ceived on the Data Downstream input for all four channels of the QSLAC device. The QSLAC de-
vice requires two of the eight GCI channels for operation. The two GCI Channels, out of the eight
possible, are determined by the S0 and S1 inputs. Data is always received with the most signifi-
cant bit first. 4 bytes of data for each GCI channel is received every 125 s at the 2.048 Mbit/s
data rate.
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