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參數(shù)資料
| 型號： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 35/95頁 |
| 文件大?。?/td> | 1399K |
| 代理商： | AM79Q062JC |
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40
Am79Q06/061/062/063 Data Sheet
mented as part of GR and the total receive path
attenuation must remain in the specified 0 to –12 dB
range. If the RG bit is set, the programmed value of GR
must not introduce more than an additional 6 dB atten-
uation.
Transmit Signal Processing
In the transmit path (A/D), the analog input signal (VIN)
is A/D converted, filtered, companded (for A-law or -
law), and made available to the PCM highway or
General Circuit Interface (GCI). Linear mode is only
available in the PCM/MPI mode. If linear form is
selected, the 16-bit data is transm itted in two
consecutive time slots starting at the programmed
time slot. The signal processor contains an ALU,
RAM, ROM, and control logic to implement the filter
se cti ons. T he B, X, and GX block s ar e us er -
programmable digital filter sections with coefficients
stored in the coefficient RAM, while AX is an analog
amplifier that can be programmed for 0 dB or 6.02 dB
gain. The B, X, and GX filters can also be operated
from an alternate set of default coefficients stored in
ROM (MPI Command 24/25, GCI Command SOP 7).
The decimator reduces the high input sampling rate to
16 kHz for input to the B, GX, and X filters. The X filter is
a six-tap FIR section that is part of the frequency
response correction network. The B filter operates on
samples from the receive signal path to provide
transhybrid balancing in the loop. The high-pass filter
rejects low frequencies such as 50 Hz or 60 Hz, and can
be disabled.
Transmit PCM Interface (PCM/MPI Mode)
In PCM/MPI mode, the transmit PCM interface
transmits a 16-bit linear code (when programmed) or an
8-bit compressed code from the digital A-law or -law
compressor. Transmit logic controls the transmission of
data onto the PCM highway through output por t
selection and time/clock slot control circuitry. The linear
data requires two consecutive time slots, while a single
time slot is required for A-law or -law data.
In the PCM Signaling mode (SMODE = 1), the transmit
time slot following the A-law or
-law data is used for
signaling information. The two time slots form a single
16-bit data block.
The frame sync (FS) pulse identifies time slot 0 of the
transmit frame and all channels (time slots) are
referenced to it. The logic contains user-programmable
Transmit Time Slot and Transmit Clock Slot registers.
The Time Slot register is 7 bits wide and allows up to 128
8-bit channels (using a PCLK of 8.192 MHz) in each
frame. This feature allows any clock frequency between
128 kHz and 8.192 MHz (2 to 128 channels) in a system.
The data is transmitted in bytes, with the most significant
bit first.
The Clock Slot register is 3 bits wide and may be
programmed to offset the time slot assignment by 0 to 7
PCLK periods to eliminate any clock skew in the system.
An exception occurs when division of the PCLK
frequency by 64 kHz produces a nonzero remainder, R,
and when the transmit clock slot is greater than R. In that
case, the R-bit fractional time slot after the last full time
slot in the frame will contain random information and will
have the TSC output turned on. For example, if the
PCLK frequency is 1.544 MHz (R = 1) and the transmit
clock slot is greater than 1, the 1-bit fractional time slot
after the last full time slot in the frame contains random
information, and the TSC output remains active during
the fractional time slot. In such cases, problems can be
avoided by simply not using the last time slot.
The PCM data can be user programmed for output onto
either the DXA or DXB port or both ports simultaneously.
Correspondingly, either TSCA or TSCB or both are Low
during transmission.
The DXA/DXB and TSCA/TSCB outputs can be
programmed to change either on the negative or positive
edge of PCLK.
Tr an smi t d a t a c a n also be r e a d t h r o u gh th e
microprocessor interface using Command 47.
Data Upstream Interface (GCI Mode)
In the GCI mode, the Data Upstream (DU) interface
transmits a total of 4 bytes per GCI channel. Two bytes
are from the A-law or -law compressor, one for voice
channel 1, one for voice channel 2, a single Monitor
channel byte, and a single SC channel byte. Transmit
logic controls the transmission of data onto the GCI bus
as determined by the frame synchronization signal
(FSC) and the S0 and S1 channel select bits. No
signaling or Linear mode options are available when
GCI mode is selected.
The frame synchronization signal (FSC) identifies GCI
channel 0 and all GCI channels are referenced to it.
Upstream Data is always transmitted at a 2.048 MHz
data rate.
Receive Signal Processing
In the receive path (D/A), the digital signal is expanded
(for A-law or -law), filtered, converted to analog, and
passed to the VOUT pin. The signal processor contains
an ALU, RAM, ROM, and Control logic to implement the
filter sections. The Z, R, and GR blocks are user-
programmable filter sections with their coefficients
stored in the coefficient RAM, while AR is an analog
amplifier that can be programmed for a 0 dB or 6.02 dB
loss. The Z, R, and GR filters can also be operated from
an alternate set of default coefficients stored in ROM
(MPI Commands 24 and 25, GCI Command SOP 7).
The low-pass filter band limits the signal. The R filter is
composed of a six-tap FIR section operating at a 16 kHz
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