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參數(shù)資料
| 型號(hào)： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 36/95頁 |
| 文件大?。?/td> | 1399K |
| 代理商： | AM79Q062JC |
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SLAC Products
41
sampling rate and a one-tap IIR section operating at
8 kHz. It is part of the frequency response correction
network. The Analog Impedance Scaling Network
(AISN) is a user-programmable gain block providing
feedback from VIN to VOUT to emulate different SLIC
input impedances from a single exter nal SLIC
impedance. The Z filter provides feedback from the
transmit signal path to the receive path and is used to
modify the effective input impedance to the system.
The interpolator increases the sampling rate prior to
D/A conversion.
Receive PCM Interface (PCM/MPI Mode)
The receive PCM interface logic controls the reception
of data bytes from the PCM highway, transfers the data
to the A-law or -law expansion logic for compressed
signals, and then passes the data to the receive path of
the signal processor. If the data received from the PCM
highway is programmed for linear code, the A-law or -
law expansion logic is bypassed and the data is
presented to the receive path of the signal processor
directly. The linear data requires two consecutive time
slots, while the A-law or
-law data requires a single
time slot.
The frame sync (FS) pulse identifies time slot 0 of the
receive frame, and all channels (time slots) are
referenced to it. The logic contains user-programmable
Receive Time Slot and Receive Clock Slot registers. The
Time Slot register is 7 bits wide and allows up to 128 8-bit
channels (using a PCLK of 8.192 MHz) in each frame.
This feature allows any clock frequency between 128 kHz
and 8.192 MHz (2 to 128 channels) in a system.
The Clock Slot register is 3 bits wide and can be
programmed to offset the time slot assignment by 0 to 7
PCLK periods to eliminate any clock skews in the
system. An exception occurs when division of the PCLK
frequency by 64 kHz produces a nonzero remainder, R,
and when the receive clock slot is greater than R. In this
case, the last full receive time slot in the frame is not
usable. For example, if the PCLK frequency is
1.544 MHz (R = 1), the receive clock slot can be only 0
or 1 if the last time slot is to be used. The PCM data can
be user-programmed for input from either the DRA or
DRB port.
Data Downstream Interface (GCI Mode)
The Data Downstream (DD) interface logic controls the
reception of data bytes from the GCI highway. The GCI
channels received by the QSLAC device is determined
by the logic levels on S0 and S1, the GCI channel select
bits. The two compressed voice channel data bytes of
the GCI channel are transferred to the A-law or -law
expansion logic. The expanded data is passed to the
receive path of the signal processor. The Monitor
channel and SC channel bytes are transferred to the
GCI control logic for processing.
The frame synchronization signal (FSC) identifies GCI
channel 0 of the GCI frame, and all other GCI channels
are referenced to it.
Downstream Data is always received at a 2.048 MHz
data rate.
Analog Impedance Scaling Network (AISN)
The AISN is incorporated in the QSLAC device to scale
the value of the external SLIC impedance. Scaling this
external impedance with the AISN (along with the Z filter)
allows matching of many different line conditions using a
single impedance value. Linecards can meet many
different specifications without any hardware changes.
The AISN is a programmable transfer function connected
from VIN to VOUT of each QSLAC device channel. The
AISN transfer function is used to alter the input imped-
ance of the SLIC device to a new value (ZIN) given by:
where G440 is the SLIC echo gain into an open circuit,
G44 is the SLIC echo gain into a short circuit, and ZSL
is the SLIC input impedance without the QSLAC device.
The gain can be varied from –0.9375 to +0.9375 in 31
steps of 0.0625. The AISN gain is determined by the
following equation:
where AISN = 0 or 1
There are two special cases to the formula for hAISN:
1) a value of AISN = 00000 specifies a gain of 0 (or
cutoff), and 2) a value of AISN = 10000 is a special case
where the AISN circuitry is disabled and VOUT is
connected internally to VIN with a gain of 0 dB. This
allows a Full Digital Loopback mode where an input
digital PCM signal is completely processed through the
receive section, looped back, processed through the
transmit section, and output as digital PCM data. During
this test, the VIN input is ignored and the VOUT output
is connected to VREF.
Speech Coding
The A/D and D/A conversion follows either the A-law
or the - l a w s t and ar d as defi ned i n IT U- T
Recommendation G.711. A-law or -law operation is
programmed using MPI Commands 24/25 or GCI
Command SOP 7. Alternate bit inversion is performed
as part of the A-law coding. In PCM/MPI mode, the
QSLAC device provides linear code as an option on both
the transmit and receive sides of the device. Linear code
is selected using MPI Commands 24 and 25. Two
successive time slots are required for linear code
operation. The linear code is a 16-bit two’s-complement
number that appears sign bit first on the PCM highway.
Linear code occupies two time slots.
ZIN
ZSL
1
G44
h
AISN
–
()
1G440 h
AISN
–
()
=
h
AISN
0.0625
=AISNi
2
i
i0
=
4
∑
16
–
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