參數(shù)資料
型號： AM79Q062JC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 編解碼器
英文描述： A/MU-LAW, PCM CODEC, PQCC32
封裝： PLASTIC, LCC-32
文件頁數(shù)： 37/95頁
文件大?。?/td> 1399K
代理商： AM79Q062JC
42
Am79Q06/061/062/063 Data Sheet
Double PCLK (DPCK) Operation
(PCM/MPI Mode)
The Double PCLK Operation allows the PCM clock
(PCLK) signal to be clocked at a rate of twice that of
the PCM data. This mode provides compatibility of the
Q S LAC de vic e wi t h other e x i s ting sy stem
architectures, such as a GCI interface system in
terminal mode operating at a 768 kHz data rate with a
1.536 MHz clock rate.
The operation is enabled by setting the DPCK bit of
Command 45 and 46 (C8/C9h). When set to zero,
operation is unchanged from normal PCM clocking
and the PCM data and clock rates are the same. When
the bit is set to 1, clocking of PCM data is divided by
two and occurs at one half of the PCLK PCM clock
rate. The internal PLL used for synchronization of the
master DSP clock (MCLK) receives its input from
either the MCLK or PCLK pin, depending on the clock
mode (CMODE) selection. If PCLK is used for MCLK
(CMODE = 1), then the clock input is routed to both the
DSP clock input and to the time slot assigner. The
timing division related to the double PCLK mode
occurs only within the time slot assigner, and therefore,
double PCLK operation is available with either
CMODE setting. This allows the MCLK/E1 pin to be
available for E1 multiplexing operation if both double
PCLK and E1 multiplexing modes are simultaneously
required.
Specifications for Double PCLK Operation are shown
in Switching Characteristics.
Signaling on the PCM Highway
(PCM/MPI Mode)
If the SMODE bit is set in the Configuration Register,
each data point occupies two consecutive time slots.
The first time slot contains A-law or
-law data and the
second time slot has the following information:
Bit 7:
Debounced CD1 bit (usually switchhook)
Bit 6:
CD2 bit or CD1B bit
Bits 5–3:
Reserved
Bit 2:
CFAIL
Bits 1–0:
Reserved
Bit 7 of the signaling byte appears immediately after bit 0
of the data byte. A-law or
-law Companded mode must
be specified in order to put signaling information on the
PCM highway. The signaling time slot remains active,
even when the channel is deactivated.
Robbed-Bit Signaling Compatibility
(PCM/MPI Mode)
The QSLAC device supports robbed bit signaling
compatibility. Robbed bit signaling allows periodic use
of the least significant bit (LSB) of the receive path
PCM data to be used to carry signaling information. In
this scheme, separate circuitry within the line card or
system intercepts this bit out of the PCM data stream
and uses this bit to control signaling functions within
the system. The QSLAC device does not perform any
processing of any of the robbed bits during this
operation; it simply allows for the robbed bit presence
by performing the LSB substitution.
If the RBE bit is set, then the robbed-bit signaling com-
patibility mode is enabled. Robbed-bit signaling is only
available in the
-law companding mode of the device.
Also, only the receive (digital-to-analog) path is in-
volved. There is no change of operation to the transmit
path and PCM data coming out of the QSLAC device
will always contain complete PCM byte data for each
time slot, regardless of robbed-bit signaling selection.
In the absence of actual PCM data for the affected time
slots, there is an uncertainty of the legitimate value of
this bit to accurately reconstruct the analog signal.
This bit can always be assumed to be a 1 or 0; hence,
the reconstructed signal is correct half the time.
However, the other half of the time, there is an
unacceptable reconstruction error of a significance
equal to the value weighting of the LSB. To reduce this
error and provide compatibility with the robbed bit
signaling scheme, when in the robbed-bit signaling
mode, the QSLAC device ignores the LSB of each
received PCM byte and replace its value in the
expander with a value of half the LSB’s weight. This
then guarantees the reconstruction is in error by only
half this LSB weight. In the expander, the eight bits of
the companded PCM byte are expanded into linear
PCM data of several more bits within the internal signal
processing path of the device. Therefore, accuracy is
not limited to the weight of the LSB, and a weight of
half this value is realizable.
When this robbed-bit mode is selected, not every
frame contains bits for signaling, and therefore not
every byte requires its LSB substituted with the half-
LSB weight. This substitution only occurs for valid
PCM time slots within frames for which this robbed bit
has been designated. To determine which time slots
are affected, the device monitors the frame sync (FS)
pulse. The current frame is a robbed-bit frame and this
half-LSB value is used only when this criteria is met:
s The RBE bit is set, and
s The device is in the
-law companding mode, and
s The current frame sync pulse (FS) is two PCLK
cycles long, and
s The previous frame sync pulse (FS) was not two
PCLK cycles long.
The frame sync pulse is sampled on the falling edge of
PCLK. As shown in Figure 13, if the above criteria is
met, and if FS is high for two consecutive falling edges
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