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參數(shù)資料
| 型號(hào)： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁(yè)數(shù)： | 63/95頁(yè) |
| 文件大?。?/td> | 1399K |
| 代理商： | AM79Q062JC |
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66
Am79Q06/061/062/063 Data Sheet
Upstream C/I Channel
The SC channel, which includes the six C/I channel bits,
is transmitted upstream every frame. The bit definitions
for the upstream C/I channel are shown below. These
bits are transmitted by the QSLAC device (Most
significant bit first).
GCI Format
<------------------------ Upstream SC Octet ------------------>
|<----------------------- C/I FIELD ------------->|
Upstream Bit Definitions of the C/I field require the
programmable I/O ports to be programmed as inputs.
Otherwise, these bits follow the downstream C/I bits for
CD1x, CD2x, and C3x.
CDAx: Debounced CD1x bit of channel x.
CDBx: The filtered CD2x bit of channel x in non-E1
demultiplexed mode or the filtered CD1Bx bit in the E1
demultiplexed mode.
C3x–C3x of channel x.
The logic state of the CDA, CDB, and C3 device pins are
read and transmitted in the upstream C/I channel only if
they are programmed as an Input. In GCI mode, C4 and
C5 are not available as upstream C/I data but can be
obtained by reading the SLIC I/O register.
Monitor Channel
The Monitor Channel (see Figure 17) is used to read
and write the QSLAC device’s coefficient registers, to
read the status of the device and the contents of the
internal registers, and to provide supplementary
signaling. Information is transferred on the Monitor
Channel using the MR and MX bits of the SC channel,
providing a secure method of data exchange between
the upstream and downstream devices.
The Monitor byte is the third byte in the 4 byte GCI
channel and is received every 125 s over the DU or DD
pins. A Monitor command consists of one address byte,
one or more command bytes, and is followed by
additional bytes of input data as required. The command
may be followed by the QSLAC device sending data
bytes upstream via the DU pin.
Monitor Channel Protocol
MSB
LSB
7
6
5
4
3
2
1
0
C31
CDB1
CDA1
C32
CDB2
CDA2
MR
MX
Figure 17. Maximum Speed Monitor Handshake Timing
Transmitter
Receiver
MX
MR
1st Byte
2nd Byte
3rd Byte
125
s
EOM
ACK
1st Byte
ACK
2nd Byte
ACK
3rd Byte
21108A-031
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