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| 型號： | AM79Q062JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 編解碼器 |
| 英文描述： | A/MU-LAW, PCM CODEC, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 32/95頁 |
| 文件大小： | 1399K |
| 代理商： | AM79Q062JC |
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38
Am79Q06/061/062/063 Data Sheet
to High or High to Low); or any time the transmit PCM
data changes on a channel where the Arm Transmit
Interrupt (ATI) bit is on. The interrupt control is shown in
Figure 9. The interrupt remains Low until the appropriate
register is read. This output can be programmed as a
TTL or open drain output by the INTM bit, MPI
Command 12 or GCI Command SOP 6. When an
interrupt is generated, all of the unmasked bits in the
Real Time Data register are latched and remain latched
until the interrupt is cleared. The interrupt is cleared by
reading the register with MPI Command 17 or GCI
Command SOP 13, by writing to the interrupt mask
register (MPI Command 26 or GCI Command SOP 14),
or by a reset. If any of the inputs to the unmasked bits in
the Real Time Data register are different from the
register bits at the time that the interrupt is cleared, a
new interrupt is immediately generated with the new
data latched into the Real Time Data register. For this
reason, the interrupt logic in the controller should be
level sensitive rather than edge sensitive.
Interrupt Mask Register
The Real Time Data register data bits can be masked
from causing an interrupt to the processor using the
interrupt mask register. The contents of the mask
register can be written or read via the MPI Commands
26 and 27 or GCI Command SOP 14.
Active State
Each channel of the QSLAC device can operate in either
the Active (operational) or Inactive (standby) mode. In
the Active mode, individual channels of the QSLAC
device can transmit and receive PCM or linear data and
analog information. The Active mode is required when a
telephone call is in progress. The Activate command,
MPI Command 5, GCI Command SOP 4, puts the
selected channels (see channel enable register for
PCM/MPI Mode) into this state. Bringing a channel of
the QSLAC device into the Active mode is only possible
through the MPI command or the GCI Command.
Inactive State
All channels of the QSLAC device are forced into the
Inactive mode by a power-up or hardware reset.
Individual channels can be programmed into this mode
by the deactivate command (MPI Command 1, GCI
Command SOP 1) or by the software reset command
(MPI Command 2, GCI Command 2). Power is
disconnected from all nonessential circuitry, while the
MPI remains active to receive commands. The analog
output is tied to VREF through a resistor whose value
depends on the VMODE bit. All circuits that contain
programmed information retain their data in the
Inactive mode.
Low Power State
If all four channels are deactivated and Low Power
mode is selected, the internal clock speed of the part will
be reduced to 1/6 of its normal speed. When this
hap pens , th e C FAIL bit is set to 1, and th e
microprocessor interface works at 1/6 its normal speed.
That is, the CS must be high six times as long between
MPI commands.
Chopper Clock
The Am79Q06 and Am79Q063 devices provide a
chopper clock output to drive the switching regulator
on some AMD S L IC s. The cl ock fr equenc y is
selectable as 256 or 292.57 kHz by the CHP bit (MPI
Command 12/GCI Command SOP 6). The chopper
output must be turned on with the ECH bit (MPI
Command 45, GCI Command SOP 11).
Reset States
The QSLAC device can be reset by application of power,
by an active Low on the hardware Reset pin (RST), by a
hardware reset command, or by
CS Low for 16 or more
rising edges of DCLK.
1.
A-law companding is selected.
2.
Default filter values B, X, R, and Z are selected and
the AISN is set to zero.
3.
Default digital gain blocks, GX and GR, are selected.
The analog gains, AX and AR, are set to 0 dB.
4.
SLIC input/outputs CD1, CD2, C3, C4, and C5 are
set to the Input mode.
5.
All of the test modes in the Operating Conditions
Register are turned off (0s).
6.
All four channels are placed in the Inactive
(standby) mode.
7.
For PCM/MPI mode, transmit time slots and receive
time slots are set to 0, 1, 2, and 3 for Channels 1, 2,
3, and 4, respectively. The clock slots are set to 0,
with transmit on the negative edge. For GCI mode,
operation is determined by S0 and S1.
8.
DXA/DU port is selected for all channels.
9.
DRA/DD port is selected for all channels.
10. The master clock frequency in PCM/MPI mode is
selected to be 8.192 MHz and is programmed to
come from PCLK. In GCI mode, DCL is 2.048 or
4.096 MHz and is determined by the QSLAC device.
11. All four channels are selected in the Channel Enable
Register for PCM/MPI mode.
12. Any pending interrupts are cleared, all interrupts are
masked, and the Interrupt Output mode is set to
open drain.
13. The supervision debounce time is set to 8 ms.
14. The previously programmed B, Z, X, R, GX, and GR
filters are unchanged.
15. The chopper clock frequency is set to 256 kHz, but
the chopper clock is turned off.
16. The E1 Multiplex mode is turned off and the polarity
is set for high going pulses.
17. No signaling on the PCM highway (PCM/MPI mode).
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