
2004 Microchip Technology Inc.
Preliminary
DS39637A-page 79
PIC18F2480/2580/4480/4580
SPBRGH
EUSART Baud Rate Generator High Byte
0000 0000
51, 231
SPBRG
EUSART Baud Rate Generator
0000 0000
51, 231
RCREG
EUSART Receive Register
0000 0000
51, 238
TXREG
EUSART Transmit Register
0000 0000
51, 236
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
51, 237
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
51, 237
EEADR
EEPROM Address Register
0000 0000
51, 105
EEDATA
EEPROM Data Register
0000 0000
51, 105
EECON2
EEPROM Control Register 2 (not a physical register)
0000 0000
51, 105
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000
51, 105
IPR3
Mode 0
IRXIP
WAKIP
ERRIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP
1111 1111
51, 126
IPR3
Mode 1, 2
IRXIP
WAKIP
ERRIP
TXBnIP
TXB1IP
(8)
TXB0IP
(8)
RXBnIP
FIFOWMIP
1111 1111
51, 126
PIR3
Mode 0
IRXIF
WAKIF
ERRIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF
0000 0000
51, 120
PIR3
Mode 1, 2
IRXIF
WAKIF
ERRIF
TXBnIF
TXB1IF
(8)
TXB0IF
(8)
RXBnIF
FIFOWMIF
0000 0000
51, 120
PIE3
Mode 0
IRXIE
WAKIE
ERRIE
TXB2IE
TXB1IE
TXB0IE
RXB1IE
RXB0IE
0000 0000
51, 123
PIE3
Mode 1, 2
IRXIE
WAKIE
ERRIE
TXBnIE
TXB1IE
(8)
TXB0IE
(8)
RXBnIE
FIFOMWIE
0000 0000
51, 123
IPR2
OSCFIP
CMIP
(9)
CMIF
(9)
CMIE
(9)
—
EEIP
BCLIP
HLVDIP
TMR3IP
ECCP1IP
(9)
ECCP1IF
(9)
ECCP1IE
(9)
11-1 1111
51, 125
PIR2
OSCFIF
—
EEIF
BCLIF
HLVDIF
TMR3IF
00-0 0000
51, 119
PIE2
OSCFIE
PSPIP
(3)
PSPIF
(3)
PSPIE
(3)
—
EEIE
BCLIE
HLVDIE
TMR3IE
00-0 0000
52, 122
IPR1
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
52, 124
PIR1
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
52, 118
PIE1
ADIE
PLLEN
(4)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
52, 121
OSCTUNE
TRISE
(3)
TRISD
(3)
INTSRC
—
TUN4
TUN3
TUN2
TUN1
TUN0
0q-0 0000
27, 52
IBF
OBF
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
0000 -111
52, 141
Data Direction Control Register for PORTD
1111 1111
52, 138
TRISC
Data Direction Control Register for PORTC
1111 1111
52, 135
TRISB
Data Direction Control Register for PORTB
TRISA7
(6)
TRISA6
(6)
1111 1111
52, 132
TRISA
LATE
(3)
LATD
(3)
Data Direction Control Register for PORTA
1111 1111
52, 129
—
—
—
—
—
LATE2
LATE1
LATE0
---- -xxx
52, 141
Read PORTD Data Latch, Write PORTD Data Latch
xxxx xxxx
52, 138
LATC
Read PORTC Data Latch, Write PORTC Data Latch
xxxx xxxx
52, 135
LATB
Read PORTB Data Latch, Write PORTB Data Latch
LATA7
(6)
LATA6
(6)
xxxx xxxx
52, 132
LATA
Read PORTA Data Latch, Write PORTA Data Latch
xxxx xxxx
52, 129
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
Legend:
x
= unknown,
u
= unchanged,
-
= unimplemented,
q
= value depends on condition
Note 1:
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2:
The SBOREN bit is only available when CONFIG2L<1:0> =
01
; otherwise it is disabled and reads as ‘
0
’. See
Section 4.4 “Brown-out Reset
(BOR)”
.
3:
These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘
0
’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4:
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘
0
’. See
Section 2.6.4 “PLL in INTOSC
Modes”
.
5:
The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> =
0
); otherwise, RE3 reads as ‘
0
’. This bit is read-only.
6:
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7:
CAN bits have multiple functions depending on the selected mode of the CAN module.
8:
This register reads all ‘
0
’s until the ECAN technology is set up in Mode 1 or Mode 2.
9:
These registers are available on PIC18F4X80 devices only.