
PIC18F2480/2580/4480/4580
DS39637A-page 388
Preliminary
2004 Microchip Technology Inc.
MULLW
Example:
MULWF
Example:
Multiply Literal with W
Syntax:
MULLW k
Operands:
0
≤
k
≤
255
(W) x k
→
PRODH:PRODL
Operation:
Status Affected:
None
Encoding:
0000
1101
kkkk
kkkk
Description:
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
W is unchanged.
None of the status flags are affected.
Note that neither overflow nor carry is
possible in this operation. A zero result
is possible but not detected.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
MULLW 0C4h
Before Instruction
W
PRODH
PRODL
After Instruction
W
PRODH
PRODL
=
=
=
E2h
=
=
=
E2h
ADh
08h
Multiply W with f
Syntax:
MULWF f {,a}
Operands:
0
≤
f
≤
255
a
∈
[0,1]
(W) x (f)
→
PRODH:PRODL
Operation:
Status Affected:
None
Encoding:
0000
001a
ffff
ffff
Description:
An unsigned multiplication is carried
out between the contents of W and the
register file location ‘f’. The 16-bit
result is stored in the PRODH:PRODL
register pair. PRODH contains the
high byte. Both W and ‘f’ are
unchanged.
None of the status flags are affected.
Note that neither overflow nor carry is
possible in this operation. A zero
result is possible but not detected.
If ‘a(chǎn)’ is ‘
0
’, the Access Bank is
selected. If ‘a(chǎn)’ is ‘
1
’, the BSR is used
to select the GPR bank (default).
If ‘a(chǎn)’ is ‘
0
’ and the extended
instruction set is enabled, this
instruction operates in Indexed Literal
Offset Addressing mode whenever
f
≤
95 (5Fh). See
Section 25.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode”
for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
MULWF REG, 1
Before Instruction
W
REG
PRODH
PRODL
After Instruction
W
REG
PRODH
PRODL
=
=
=
=
C4h
B5h
=
=
=
=
C4h
B5h
8Ah
94h