
PIC18F2480/2580/4480/4580
DS39637A-page 54
Preliminary
2004 Microchip Technology Inc.
TXB0D5
TXB0D4
TXB0D3
TXB0D2
TXB0D1
TXB0D0
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
TXB0SIDH
TXB0CON
TXB1D7
TXB1D6
TXB1D5
TXB1D4
TXB1D3
TXB1D2
TXB1D1
TXB1D0
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
TXB2D7
TXB2D6
TXB2D5
TXB2D4
TXB2D3
TXB2D2
Legend:
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as ‘
0
’,
q
= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 4-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘
0
’.
This register reads all ‘
0
’s until ECAN technology is set up in Mode 1 or Mode 2.
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-x-- xxxx
-u-- uuuu
-u-- uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
xxx- x-xx
uuu- u-uu
uuu- u-uu
xxxx xxxx
0000 0-00
uuuu uuuu
0000 0-00
uuuu uuuu
uuuu u-uu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
-x-- xxxx
uuuu uuuu
-u-- uuuu
uuuu uuuu
-u-- uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxx- x-xx
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuu- uu-u
xxxx xxxx
uuuu uuuu
-uuu uuuu
0000 0-00
xxxx xxxx
0000 0-00
uuuu uuuu
uuuu u-uu
0uuu uuuu
xxxx xxxx
uuuu uuuu
0uuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
0uuu uuuu
0uuu uuuu
xxxx xxxx
uuuu uuuu
0uuu uuuu
xxxx xxxx
uuuu uuuu
0uuu uuuu
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET
Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Note 1:
2:
3:
4:
5:
6: