
2004 Microchip Technology Inc.
Preliminary
DS39637A-page 343
PIC18F2480/2580/4480/4580
24.0
SPECIAL FEATURES OF
THE CPU
PIC18F2480/2580/4480/4580 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These are:
Oscillator Selection
Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
Fail-Safe Clock Monitor
Two-Speed Start-up
Code Protection
ID Locations
In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in
Section 2.0
“Oscillator Configurations”
.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2480/2580/4480/
4580 devices have a Watchdog Timer, which is either
permanently enabled via the configuration bits or
software controlled (if configured as disabled).
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate configuration register bits.
24.1
Configuration Bits
The configuration bits can be programmed (read as ‘
0
’)
or left unprogrammed (read as ‘
1
’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
Programming the configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the configuration register. In normal operation mode,
a
TBLWT
instruction with the TBLPTR pointing to the
configuration register sets up the address and the data
for the configuration register write. Setting the WR bit
starts a long
write to the configuration register. The
configuration registers are written a byte at a time. To
write or erase a configuration cell, a
TBLWT
instruction
can write a ‘
1
’ or a ‘
0
’ into the cell. For additional details
on Flash programming, refer to
Section 6.5 “Writing
to Flash Program Memory”
.
TABLE 24-1:
CONFIGURATION BITS AND DEVICE IDs
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
300001h
CONFIG1H
IESO
FCMEN
—
—
FOSC3
FOSC2
FOSC1
FOSC0
00-- 0111
300002h
300003h
300005h
CONFIG2L
CONFIG2H
CONFIG3H
—
—
—
—
—
—
—
—
BORV1
WDTPS3
—
BORV0
WDTPS2
—
BOREN1
WDTPS1
LPT1OSC PBADEN
BOREN0
WDTPS0
PWRTEN
WDTEN
—
---1 1111
---1 1111
MCLRE
1--- -01-
300006h
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
3FFFFEh
3FFFFFh
Legend:
CONFIG4L
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
DEVID1
DEVID2
x
= unknown,
u
= unchanged, - = unimplemented,
q
= value depends on condition.
Shaded cells are unimplemented, read as ‘
0
’.
See Register 24-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
DEBUG
—
CPD
—
WRTD
—
—
DEV2
DEV10
XINST
—
CPB
—
WRTB
—
EBTRB
DEV1
DEV9
—
—
—
—
BBSIZ
—
—
—
—
—
—
REV4
DEV7
—
CP3
—
WRT3
—
EBTR3
—
REV3
DEV6
LVP
CP2
—
WRT2
—
EBTR2
—
REV2
DEV5
—
CP1
—
WRT1
—
EBTR1
—
REV1
DEV4
STVREN
CP0
—
WRT0
—
EBTR0
—
REV0
DEV3
10-0 -1-1
---- 1111
11-- ----
---- 1111
WRTC
—
—
DEV0
DEV8
111- ----
---- 1111
-1-- ----
xxxx xxxx
(1)
0000 1100
Note
1: