
2004 Microchip Technology Inc.
Preliminary
DS39637A-page 393
PIC18F2480/2580/4480/4580
RETURN
Example:
RLCF
Example:
Return from Subroutine
Syntax:
RETURN {s}
Operands:
s
∈
[0,1]
(TOS)
→
PC,
if s =
1
(WS)
→
W,
(STATUSS)
→
Status,
(BSRS)
→
BSR,
PCLATU, PCLATH are unchanged
Operation:
Status Affected:
None
Encoding:
0000
0000
0001
001s
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’=
1
, the contents of the shadow
registers, WS, STATUSS and BSRS,
are loaded into their corresponding
registers, W, Status and BSR. If
‘s’ =
0
, no update of these registers
occurs (default).
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
No
Q3
Q4
Decode
operation
No
operation
Process
Data
No
operation
POP PC
from stack
No
operation
No
operation
RETURN
After Interrupt
PC = TOS
Rotate Left f through Carry
Syntax:
RLCF f {,d {,a}}
Operands:
0
≤
f
≤
255
d
∈
[0,1]
a
∈
[0,1]
(f<n>)
→
dest<n + 1>,
(f<7>)
→
C,
(C)
→
dest<0>
Operation:
Status Affected:
C, N, Z
Encoding:
0011
01da
ffff
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘
0
’, the result is placed in
W. If ‘d’ is ‘
1
’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘
0
’, the Access Bank is
selected. If ‘a’ is ‘
1
’, the BSR is used to
select the GPR bank (default).
If ‘a’ is ‘
0
’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f
≤
95 (5Fh). See
Section 25.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode”
for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
RLCF
REG, 0, 0
Before Instruction
REG
C
After Instruction
REG
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
C
register f