
2004 Microchip Technology Inc.
Preliminary
DS39637A-page 295
PIC18F2480/2580/4480/4580
REGISTER 23-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE
[0
≤
n
≤
5, TXnEN (BSEL0<n>) =
1
]
(1)
R/W-0
R-0
R-0
TXBIF
TXABT
TXLARB
bit 7
R-0
R/W-0
TXREQ
R/W-0
RTREN
R/W-0
TXPRI1
R/W-0
TXPRI0
TXERR
bit 0
bit 7
TXBIF:
Transmit Buffer Interrupt Flag bit
(3)
1
= A message is successfully transmitted
0
= No message was transmitted
TXABT:
Transmission Aborted Status bit
(3)
1
= Message was aborted
0
= Message was not aborted
TXLARB:
Transmission Lost Arbitration Status bit
(3)
1
= Message lost arbitration while being sent
0
= Message did not lose arbitration while being sent
TXERR:
Transmission Error Detected Status bit
(3)
1
= A bus error occurred while the message was being sent
0
= A bus error did not occur while the message was being sent
TXREQ:
Transmit Request Status bit
(2,4)
1
= Requests sending a message; clears the TXABT, TXLARB and TXERR bits
0
= Automatically cleared when the message is successfully sent
RTREN:
Automatic Remote Transmission Request Enable bit
1
= When a remote transmission request is received, TXREQ will be automatically set
0
= When a remote transmission request is received, TXREQ will be unaffected
TXPRI1:TXPRI0:
Transmit Priority bits
(5)
11
= Priority Level 3 (highest priority)
10
= Priority Level 2
01
= Priority Level 1
00
= Priority Level 0 (lowest priority)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
These registers are available in Mode 1 and 2 only.
2:
Clearing this bit in software while the bit is set will request a message abort.
3:
This bit is automatically cleared when TXREQ is set.
4:
While TXREQ is set or transmission is in progress, transmit buffer registers remain
read-only.
5:
These bits set the order in which the transmit buffer will be transferred. They do not
alter the CAN message identifier.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown