
2004 Microchip Technology Inc.
Preliminary
DS39637A-page 55
PIC18F2480/2580/4480/4580
TXB2D1
TXB2D0
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
RXM1EIDL
RXM1EIDH
RXM1SIDL
RXM1SIDH
RXM0EIDL
RXM0EIDH
RXM0SIDL
RXM0SIDH
RXF5EIDL
RXF5EIDH
RXF5SIDL
RXF5SIDH
RXF4EIDL
RXF4EIDH
RXF4SIDL
RXF4SIDH
RXF3EIDL
RXF3EIDH
RXF3SIDL
RXF3SIDH
RXF2EIDL
RXF2EIDH
RXF2SIDL
RXF2SIDH
Legend:
2480 2580 4480 4580
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2480 2580 4480 4580
2480 2580 4480 4580
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2480 2580 4480 4580
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u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as ‘
0
’,
q
= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 4-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘
0
’.
This register reads all ‘
0
’s until ECAN technology is set up in Mode 1 or Mode 2.
xxxx xxxx
uuuu uuuu
0uuu uuuu
xxxx xxxx
-x-- xxxx
uuuu uuuu
-u-- uuuu
0uuu uuuu
-u-- uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxxx x-xx
uuuu uuuu
uuuu u-uu
uuuu uuuu
-uuu uuuu
xxx- x-xx
uuu- u-uu
uuu- u-uu
0000 0-00
xxxx xxxx
0000 0-00
uuuu uuuu
uuuu u-uu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxx- x-xx
xxxx xxxx
uuu- u-uu
uuuu uuuu
uuu- u-uu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxx- x-xx
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuu- u-uu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
xxx- x-xx
uuu- u-uu
uuu- u-uu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxx- x-xx
xxxx xxxx
uuu- u-uu
uuuu uuuu
uuu- u-uu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxx- x-xx
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuu- u-uu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
xxx- x-xx
uuu- u-uu
uuu- u-uu
xxxx xxxx
uuuu uuuu
uuuu uuuu
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET
Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Note 1:
2:
3:
4:
5:
6: