
2004 Microchip Technology Inc.
Preliminary
DS39637A-page 173
PIC18F2480/2580/4480/4580
16.0
ENHANCED
CAPTURE/COMPARE/PWM
(ECCP) MODULE
In PIC18F4480/4580 devices, ECCP1 is implemented
as a standard CCP module with Enhanced PWM
capabilities. These include the provision for 2 or 4
output channels, user selectable polarity, dead-band
control and automatic shutdown and restart. The
Enhanced features are discussed in detail in
Section 16.4 “Enhanced PWM Mode”
. Capture,
Compare and single-output PWM functions of the
ECCP module are the same as described for the
standard CCP module.
The control register for the Enhanced CCP module is
shown in Register 16-1. It differs from the CCP1CON
register in PIC18F2480/2580 devices in that the two
Most Significant bits are implemented to control PWM
functionality.
REGISTER 16-1:
ECCP1CON REGISTER (ECCP1 MODULE, PIC18F4480/4580 DEVICES)
R/W-0
R/W-0
R/W-0
R/W-0
EPWM1M1
EPWM1M0
EDC1B1
EDC1B0
bit 7
Note:
The ECCP1 module is implemented only
in PIC18F4X80 (40/44-pin) devices.
R/W-0
ECCP1M3
R/W-0
ECCP1M2
R/W-0
ECCP1M1
R/W-0
ECCP1M0
bit 0
bit 7-6
EPWM1M1:EPWM1M0:
Enhanced PWM Output Configuration bits
If ECCP1M3:ECCP1M2 =
00
,
01
,
10
:
xx
= P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If ECCP1M3:ECCP1M2 =
11
:
00
= Single output: P1A modulated, P1B, P1C, P1D assigned as port pins
01
= Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10
= Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned
as port pins
11
= Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
EDC1B1:EDC1B0
: Enhanced PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found
in CCPRxL.
ECCP1M3:ECCP1M0
: Enhanced CCP Mode Select bits
0000
= Capture/Compare/PWM off (resets ECCP module)
0001
= Reserved
0010
= Compare mode, toggle output on match
0011
= Reserved
0100
= Capture mode, every falling edge
0101
= Capture mode, every rising edge
0110
= Capture mode, every 4th rising edge
0111
= Capture mode, every 16th rising edge
1000
= Compare mode, initialize ECCP pin low, set output on compare match (set ECCP1IF)
1001
= Compare mode, initialize ECCP pin high, clear output on compare match (set ECCP1IF)
1010
= Compare mode, generate software interrupt only, CCP pin reverts to I/O state
1011
= Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets ECCP1IF bit and
starts the A/D conversion on ECCP1 match)
1100
= PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101
= PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110
= PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111
= PWM mode; P1A, P1C active-low; P1B, P1D active-low
bit 5-4
bit 3-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown