
PIC18F2480/2580/4480/4580
DS39637A-page 52
Preliminary
2004 Microchip Technology Inc.
PIE2
2480 2580 4480 4580
2480 2580 4480 4580
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2480 2580 4480 4580
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2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
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u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as ‘
0
’,
q
= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 4-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘
0
’.
This register reads all ‘
0
’s until ECAN technology is set up in Mode 1 or Mode 2.
00-0 0000
00-0 0000
uu-u uuuu
0--0 000-
1111 1111
0--0 000-
1111 1111
u--u uuu-
uuuu uuuu
IPR1
-111 1111
-111 1111
-uuu uuuu
uuuu uuuu
(1)
-uuu uuuu
PIR1
0000 0000
-000 0000
0000 0000
-000 0000
PIE1
0000 0000
0000 0000
uuuu uuuu
-000 0000
--00 0000
-000 0000
--00 0000
-uuu uuuu
--uu uuuu
OSCTUNE
TRISE
TRISD
TRISC
TRISB
TRISA
(5)
LATE
LATD
LATC
LATB
LATA
(5)
PORTE
PORTD
PORTC
PORTB
PORTA
(5)
ECANCON
TXERRCNT
RXERRCNT
COMSTAT
CIOCON
BRGCON3
BRGCON2
BRGCON1
Legend:
0000 -111
0000 -111
uuuu -uuu
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
1111 1111
1111 1111
(5)
---- -xxx
1111 1111
1111 1111
(5)
---- -uuu
uuuu uuuu
uuuu uuuu
(5)
---- -uuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxxx xxxx
xxxx xxxx
(5)
uuuu uuuu
uuuu uuuu
uuuu uuuu
(5)
uuuu uuuu
uuuu uuuu
uuuu uuuu
(5)
---- x000
xxxx xxxx
---- x000
uuuu uuuu
---- uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xx0x 0000
(5)
uuuu uuuu
uu0u 0000
(5)
uuuu uuuu
uuuu uuuu
(5)
0001 0000
0001 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
--00 ----
00-- -000
--00 ----
00-- -000
--uu ----
uu-- -uuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET
Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Note 1:
2:
3:
4:
5:
6: