
PIC18F2480/2580/4480/4580
DS39637A-page 50
Preliminary
2004 Microchip Technology Inc.
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
Legend:
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2480 2580 4480 4580
2480 2580 4480 4580
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2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
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2480 2580 4480 4580
u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as ‘
0
’,
q
= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 4-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘
0
’.
This register reads all ‘
0
’s until ECAN technology is set up in Mode 1 or Mode 2.
---- 0000
N/A
N/A
N/A
N/A
N/A
---- 0000
N/A
N/A
N/A
N/A
N/A
---- uuuu
N/A
N/A
N/A
N/A
N/A
---- 0000
---- 0000
---- uuuu
xxxx xxxx
---x xxxx
uuuu uuuu
---u uuuu
uuuu uuuu
---u uuuu
0000 0000
0000 0000
uuuu uuuu
xxxx xxxx
1111 1111
uuuu uuuu
1111 1111
uuuu uuuu
uuuu uuuu
0100 q000
0100 00q0
uuuu uuqu
0-00 0101
---- ---0
0-00 0101
---- ---0
0-uu uuuu
---- ---u
0q-1 11q0
0q-q qquu
uq-u qquu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
u0uu uuuu
uuuu uuuu
0000 0000
1111 1111
0000 0000
1111 1111
uuuu uuuu
1111 1111
-000 0000
-000 0000
-uuu uuuu
xxxx xxxx
0000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
--00 0000
uuuu uuuu
--00 0000
uuuu uuuu
--uu uuuu
--00 0qqq
--00 0qqq
--uu uuuu
0-00 0000
0-00 0000
u-uu uuuu
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET
Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Note 1:
2:
3:
4:
5:
6: