
PIC18F2480/2580/4480/4580
DS39637A-page 396
Preliminary
2004 Microchip Technology Inc.
SLEEP
Example:
SUBFWB
Enter Sleep mode
Syntax:
SLEEP
Operands:
None
Operation:
00h
→
WDT,
0
→
WDT postscaler,
1
→
TO,
0
→
PD
Status Affected:
TO, PD
Encoding:
0000
0000
0000
0011
Description:
The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
No
Q3
Q4
Decode
operation
Process
Data
Go to
Sleep
SLEEP
Before Instruction
TO
PD =
After Instruction
TO
PD =
=
=
1
0
If WDT causes wake-up, this bit is cleared.
Subtract f from W with Borrow
Syntax:
SUBFWB f {,d {,a}}
Operands:
0
≤
f
≤
255
d
∈
[0,1]
a
∈
[0,1]
(W) – (f) – (C)
→
dest
Operation:
Status Affected:
N, OV, C, DC, Z
Encoding:
0101
01da
ffff
ffff
Description:
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘
0
’, the result is stored
in W. If ‘d’ is ‘
1
’, the result is stored in
register ‘f’ (default).
If ‘a(chǎn)’ is ‘
0
’, the Access Bank is selected.
If ‘a(chǎn)’ is ‘
1
’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘
0
’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
≤
95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
Before Instruction
REG
W
C
After Instruction
REG
W
C
Z
N
Example 2:
Before Instruction
REG
W
C
After Instruction
REG
W
C
Z
N
Example 3:
Before Instruction
REG
W
C
After Instruction
REG
W
C
Z
N
SUBFWB REG, 1, 0
=
=
=
3
2
1
=
=
=
=
=
FF
2
0
0
1 ; result is negative
SUBFWB REG, 0, 0
=
=
=
2
5
1
=
=
=
=
=
2
3
1
0
0 ; result is positive
SUBFWB REG, 1, 0
=
=
=
1
2
0
=
=
=
=
=
0
2
1
1 ; result is zero
0