
2004 Microchip Technology Inc.
Preliminary
DS39637A-page 261
PIC18F2480/2580/4480/4580
20.9
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to V
DD
and V
SS
. The analog input, therefore, must be between
V
SS
and V
DD
. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 k
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 20-4:
COMPARATOR ANALOG INPUT MODEL
TABLE 20-1:
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
VA
R
S
< 10k
A
IN
C
PIN
5 pF
V
DD
V
T
= 0.6V
V
T
= 0.6V
R
IC
I
LEAKAGE
±500 nA
V
SS
Legend:
C
PIN
V
T
I
LEAKAGE
= Leakage Current at the pin due to various junctions
R
IC
= Interconnect Resistance
R
S
= Source Impedance
VA
= Analog Voltage
= Input Capacitance
= Threshold Voltage
Comparator
Input
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
CMCON
(3)
CVRCON
(3)
INTCON
IPR2
PIR2
PIE2
PORTA
LATA
TRISA
Legend:
Note 1:
C2OUT
CVREN
GIE/GIEH PEIE/GIEL
OSCFIP
OSCFIF
OSCFIE
RA7
(1)
LATA7
(1)
TRISA7
(1)
— = unimplemented, read as ‘
0
’. Shaded cells are unused by the comparator module.
PORTA pins are enabled based on oscillator configuration.
These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices.
These registers are unimplemented on PIC18F2X80 devices.
C1OUT
CVROE
C2INV
CVRR
TMR0IE
—
—
—
RA5
LATA Data Output Register
TRISA6
(1)
PORTA Data Direction Register
C1INV
CVRSS
INT0IE
EEIP
EEIF
EEIE
RA4
CIS
CVR3
RBIE
BCLIP
BCLIF
BCLIE
RA3
CM2
CVR2
TMR0IF
HLVDIP
HLVDIF
HLVDIE
RA2
CM1
CVR1
INT0IF
TMR3IP
TMR3IF
TMR3IE
RA1
CM0
CVR0
RBIF
ECCP1IP
ECCP1IF
ECCP1IE
RA0
51
51
52
51
51
52
52
52
52
CMIP
(2)
CMIF
(2)
CMIE
(2)
RA6
(1)
LATA6
(1)
2:
3: