
2004 Microchip Technology Inc.
Preliminary
DS39637A-page 59
PIC18F2480/2580/4480/4580
BSEL0
(6)
MSEL3
(6)
MSEL2
(6)
MSEL1
(6)
MSEL0
(6)
SDFLC
(6)
RXFCON1
(6)
RXFCON0
(6)
RXFBCON7
(6)
RXFBCON6
(6)
RXFBCON5
(6)
RXFBCON4
(6)
RXFBCON3
(6)
RXFBCON2
(6)
RXFBCON1
(6)
RXFBCON0
(6)
RXF15EIDL
(6)
RXF15EIDH
(6)
RXF15SIDL
(6)
RXF15SIDH
(6)
RXF14EIDL
(6)
RXF14EIDH
(6)
RXF14SIDL
(6)
RXF14SIDH
(6)
RXF13EIDL
(6)
RXF13EIDH
(6)
RXF13SIDL
(6)
RXF13SIDH
(6)
RXF12EIDL
(6)
RXF12EIDH
(6)
RXF12SIDL
(6)
Legend:
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as ‘
0
’,
q
= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 4-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘
0
’.
This register reads all ‘
0
’s until ECAN technology is set up in Mode 1 or Mode 2.
0000 00--
0000 00--
uuuu uu--
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0101
0000 0000
0000 0101
uuuu uuuu
uuuu uuuu
0101 0000
0101 0000
uuuu uuuu
---0 0000
0000 0000
---0 0000
0000 0000
-u-- uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0001 0001
0001 0001
uuuu uuuu
0001 0001
0000 0000
0001 0001
0000 0000
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxx- x-xx
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuu- u-uu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
xxx- x-xx
uuu- u-uu
uuu- u-uu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxx- x-xx
xxxx xxxx
uuu- u-uu
uuuu uuuu
uuu- u-uu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
xxx- x-xx
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuu- u-uu
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET
Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Note 1:
2:
3:
4:
5:
6: