
2004 Microchip Technology Inc.
Preliminary
DS39637A-page 103
PIC18F2480/2580/4480/4580
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during nor-
mal operation, the user can check the WRERR bit and
rewrite the location(s) as needed.
6.5.4
PROTECTION AGAINST SPURIOUS
WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See
Section 24.0 “Special Features of the
CPU”
for more detail.
6.6
Flash Program Operation During
Code Protection
See
Section 24.5 “Program Verification and Code
Protection”
for details on code protection of Flash
program memory.
TABLE 6-2:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
PROGRAM_MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DECFSZ
BRA
BSF
BCF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
COUNTER1
WRITE_BUFFER_BACK
INTCON, GIE
EECON1, WREN
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
Required
Sequence
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
page
TBLPTRU
TBPLTRH
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
Note 1:
—
—
bit21
(3)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer High Byte (TBLPTR<7:0>)
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
INTE
EEPROM Control Register 2 (not a physical register)
EEPGD
CFGS
—
FREE
WRERR
OSCFIP
CMIP
(2)
—
EEIP
OSCFIF
CMIF
(2)
—
EEIF
OSCFIE
CMIE
(2)
—
EEIE
— = unimplemented, read as ‘
0
’. Shaded cells are not used during Flash/EEPROM access.
These bits are available in PIC18F4X80 devices only.
These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices.
This bit is available only in serial programming.
49
49
49
49
49
51
51
51
51
52
RBIE
TMR0IF
INTF
RBIF
WREN
HLVDIP
HLVDIF
HLVDIE
WR
RD
BCLIP
BCLIF
BCLIE
TMR3IP
TMR3IF
TMR3IE
ECCP1IP
(1)
ECCP1IF
(1)
ECCP1IE
(1)
2:
3: