參數(shù)資料
型號(hào)： W948D6FBHX6G
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： DRAM
英文描述： 8M X 16 DDR DRAM, 5 ns, PBGA60
封裝： 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60
文件頁(yè)數(shù)： 8/60頁(yè)
文件大?。?/td> 1147K
代理商： W948D6FBHX6G
W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 16 -
Revision A01-003
6.6.1 Extended Mode Register Definition
Extended Mode Reg.
Address Bus
A0
A1
A2
A3
A4
A5
A7 ~
An....A8 (1)
BA0
BA1
1
0
0 ( 2)
DS
Reserved
PASR
A6
A5
Drive Strength
0
1
0
Full Strength Driver
Half Strength Drive
Quarter Strength Driver
A2
A1
A0
PASR
0
1
All banks
1/2 array (BA1=0)
1/4 array (BA1=BA0=0)
Reserved
NOTES:
1.MSB depends on mobile DDR SDRAM density.
2.A logic 0 should be programmed to all unused / undefined bits to ensure future compatibility.
Octant Strength Driver
A7
0
1
0
Three-Quarters Strength Driver
6.7 Status Register Read
Status Register Read (SRR) is an optional feature in JEDEC, and it is implemented in this device. With SRR, a
method is defined to read registers from the device. The encoding for an SRR command is the same as a MRS with
BA[1:0]=”01”. The address pins (A[n:0]) encode which register is to be read. Currently only one register is defined at
A[n:0]=0. The sequence to perform an SRR command is as follows:
All reads/writes must be completed
All banks must be closed
MRS with BA=01 is issued (SRR)
Wait tSRR
Read issued to any bank/page
CAS latency cycles later the device returns the registers data as it would a normal read
The next command to the device can be issued tSRC after the Read command was issued.
The burst length for the SRR read is always fixed to length 2.
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