參數(shù)資料
型號: W948D6FBHX6G
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 8M X 16 DDR DRAM, 5 ns, PBGA60
封裝: 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60
文件頁數(shù): 31/60頁
文件大?。?/td> 1147K
代理商: W948D6FBHX6G
W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 37 -
Revision A01-003
7.6.7 Random Write Cycles
Full-speed random write accesses within a page or pages can be performed as shown in figure below.
BA,Col n
BA,Col b
WRITE
NOP
CK
Command
Address
1) Dl b etc.= Data in to column b, etc.;
b’, etc.= the next Data In following Dl b, etc. according to the programmed burst order
2) Programmed burst length = 2, 4, 8 or 16 in cases shown. If burst of 4,8 or 16, burst would be truncated
3) Each WRITE command may be to any active bank and may be to the same or different devices.
WRITE
= Don't Care
DQS
DQ
DM
tDQSSmax
BA,Col a
BA,Col x
BA,Col n
BA,Col g
Di b
Di b’
Di x
Di x’
Di n
Di n’
Di a
Di a’
7.6.8 Write to Read
Data for any Write burst may be followed by a subsequent READ command.
7.6.9 Non-Interrupting Write to Read
To follow a Write without truncating the write burst, tWTR should be met as shown in the figure below.
BA,Col b
WRITE
NOP
CK
Command
Address
1) Dl b = Data in to column b
3 subsequent elements of Data In are applied in the programmed order following DI b.
2) A non-interrupted burst of 4 is shown.
3) tWTR is referenced from the positive clock edge after the last Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) The READ and WRITE commands are to the same device but not necessarily to the same bank.
NOP
READ
= Don't Care
DQS
DQ
DM
tDQSSmax
BA,Col n
tWTR
CL=3
DI b
NOP
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