參數(shù)資料
型號(hào): W948D6FBHX6G
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 8M X 16 DDR DRAM, 5 ns, PBGA60
封裝: 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60
文件頁(yè)數(shù): 20/60頁(yè)
文件大?。?/td> 1147K
代理商: W948D6FBHX6G
W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 27 -
Revision A01-003
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum time interval between two successive ACTIVE commands
on different banks is defined by tRRD.
The row remains active until a PRECHARGE command (or READ or WRITE command with Auto Precharge) is
issued to the bank.
A PRECHARGE (or READ with Auto Precharge or Write with Auto Precharge) command must be issued before
opening a different row in the same bank.
7.4.2 Bank Activation Command Cycle
NOP
ACT
NOP
RD/WR
Row
Col
BA x
BA y
tRCD
tRRD
= Don't Care
CK
Command
A0-An
BA0,BA1
7.5. Read
The READ command is used to initiate a burst read access to an active row, with a burst length as set in the Mode
Register. BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10
determines whether or not Auto Pre-charge is used. If Auto Pre-charge is selected, the row being accessed will be
pre-charged at the end of the read burst; if Auto Pre-charge is not selected, the row will remain open for subsequent
accesses.
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