參數(shù)資料
型號： W948D6FBHX6G
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 8M X 16 DDR DRAM, 5 ns, PBGA60
封裝： 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60
文件頁數(shù)： 50/60頁
文件大?。?/td> 1147K
代理商： W948D6FBHX6G
W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 54 -
Revision A01-003
19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters
are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins
driving (LZ).
20. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output
drivers for any given cycle.
21. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before
the corresponding CK edge. A valid transition is defined as monotonic and meeting the input slew rate
specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning
from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
22. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
23. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-
down element in the system. It is recommended to turn off the weak pull-down element during read and write
bursts (DQS drivers enabled).
24. At least one clock cycle is required during tWR time when in auto precharge mode.
25. Minimum 3 clocks of tDAL (=tWR + tRP) is required because it need minimum 2 clocks for tWR and minimum
1 clock for tRP.
tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next higher
integer.
26. There must be at least two clock pulses during the tXSR period.
27. There must be at least one clock pulse during the tXP period.
28. tREFI values are dependence on density and bus width.
29. A maximum of 8 Refresh commands can be posted to any given M, meaning that the maximum absolute
interval between any Refresh command and the next Refresh command is 8*tREFI.
8.5.1 CAS Latency Definition (With CL=3)
CL=3
tLZmin
tRPRE
tDQSCKmin
tRPST
T5n
T5
T4n
T3n
T2n
T4
T3
T2
READ
NOP
Command
CK
DQS
All DQ,
collectively
1)DQ transitioning after DQS transition define tDQSQ window.
2)ALL DQ must transition by tDQSQ after DQS transitions, regardless of tAC
3)tAC is the DQ output window relative to CK,and is the long term component of DQ skew.
T0
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
tLZmin
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