參數(shù)資料
型號(hào)： W948D6FBHX6G
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 8M X 16 DDR DRAM, 5 ns, PBGA60
封裝： 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60
文件頁(yè)數(shù)： 4/60頁(yè)
文件大?。?/td> 1147K
代理商： W948D6FBHX6G
W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 12 -
Revision A01-003
6.1.2 Initialization Waveform Sequence
VDD
VDDQ
CK
CKE
Command
Address
A10
BA0,BA1
DM
DQ,DQS
200us
tCK
tRP
tRFC
tMRD
NOP
PRE
ARF
MRS
ACT
CODE
RA
BA
BA0=L
BA1=L
BA0=L
BA1=H
All
Banks
(High-Z)
VDD/VDDQ powered up
Clock stable
Load
Mode Reg.
Load
Ext.Mode Reg..
= Don't Care
6.2 Register Definition
6.2.1 Mode Register Set Operation
The Mode Register is used to define the specific mode of operation of the LPDDR SDRAM. This definition includes
the definition of a burst length, a burst type, a CAS latency as shown in the following figure.
The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and BA1=0) and will
retain the stored information until it is reprogrammed, the device goes into Deep Power Down mode, or the device
loses power.
Mode Register bits A0-A2 specify the burst length, A3 the type of burst (sequential or interleave), A4-A6 the CAS
latency. A logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility.
The Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must
wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
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