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參數(shù)資料
| 型號： | W948D6FBHX6G |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 5 ns, PBGA60 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60 |
| 文件頁數(shù)： | 2/60頁 |
| 文件大?。?/td> | 1147K |
| 代理商： | W948D6FBHX6G |
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W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 10 -
Revision A01-003
6. FUNCTION DESCRIPTION
6.1 Initialization
LPDDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures other than
those specified may result in undefined operation. If there is any interruption to the device power, the initialization
routine should be followed. The steps to be followed for device initialization are listed below.
The Mode Register and Extended Mode Register do not have default values. If they are not programmed during the
initialization sequence, it may lead to unspecified operation. The clock stop feature is not available until the device
has been properly initialized from Step 1 through 11.
Step 1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up
simultaneously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ
are from the same power source. Also Assert and hold Clock Enable (CKE) to a LVCMOS logic high level
Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to apply
stable clock.
Step 3: There must be at least 200
μs of valid clocks before any command may be given to the DRAM. During this
time NOP or DESELECT commands must be issued on the command bus.
Step 4: Issue a PRECHARGE ALL command.
Step 5: Provide NOPs or DESELECT commands for at least tRP time.
Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time.
Issue the second AUTO REFRESH command followed by NOPs or DESELECT command for at least
tRFC time. Note as part of the initialization sequence there must be two Auto Refresh commands issued.
The typical flow is to issue them at Step 6, but they may also be issued between steps 10 and 11.
Step 7: Using the MRS command, program the base mode register. Set the desired operation modes.
Step 8: Provide NOPs or DESELECT commands for at least tMRD time.
Step 9: Using the MRS command, program the extended mode register for the desired operating modes. Note the
order of the base and extended mode register programmed is not important.
Step 10: Provide NOP or DESELECT commands for at least tMRD time.
Step 11: The DRAM has been properly initialized and is ready for any valid command.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W949D2CB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512Mb Mobile LPDDR |
| W949D2CBJX5E | 功能描述:IC LPDDR SDRAM 512MBIT 90VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| W949D2CBJX5ETR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ |
| W949D2CBJX5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip Mobile LPDDR SDRAM 512M-Bit 16Mx32 1.8V 90-Pin VFBGA |
| W949D2CBJX5I TR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ, INDUST |
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