- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄202135 > W948D6FBHX6G (WINBOND ELECTRONICS CORP) 8M X 16 DDR DRAM, 5 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號： | W948D6FBHX6G |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 5 ns, PBGA60 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60 |
| 文件頁數(shù)： | 33/60頁 |
| 文件大?。?/td> | 1147K |
| 代理商： | W948D6FBHX6G |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 39 -
Revision A01-003
7.6.13 Interrupting Write to Precharge
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in figure below.
Note that only data-in pairs that are registered prior to the tWR period are written to the internal array, and any
subsequent data-in should be masked with DM, as shown in figure. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until tRP is met.
BA,Col n
BA a(or
all)
BA,Col b
WRITE
PRE
NOP
CK
Command
Address
1) Dl b = Data in to column b.
2) An interrupted burst of 4, 8 or 16 is shown, 2 data elements are written.
3) tWR is referenced from the positive clock edge after the last desired Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) *1=can be Don't Care for programmed burst length of 4
6) *2=for programmed burst length of 4, DQS becomes Don't Care at this point
NOP
= Don't Care
DQS
DQ
DM
tDQSSmax
tWR
DI b
*1
*2
7.7 Precharge
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is
issued.
Input A10 determines whether one or all banks are to be precharged. In case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Dont Care”.
Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE
command being issued. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if
the previously open row is already in the process of precharging.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WF128K32-120HC5 | 512K X 8 FLASH 5V PROM MODULE, 120 ns, CHIP66 |
| WF128K32-90HM5 | 512K X 8 FLASH 5V PROM MODULE, 90 ns, CHIP66 |
| WS128K32-35CJM | 512K X 8 MULTI DEVICE SRAM MODULE, 35 ns, CQCC68 |
| WS512K32F-100G2Q | 2M X 8 MULTI DEVICE SRAM MODULE, 100 ns, QMA68 |
| WMS128K8L-100DJIE | 128K X 8 STANDARD SRAM, 100 ns, CDSO36 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W949D2CB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512Mb Mobile LPDDR |
| W949D2CBJX5E | 功能描述:IC LPDDR SDRAM 512MBIT 90VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| W949D2CBJX5ETR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ |
| W949D2CBJX5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip Mobile LPDDR SDRAM 512M-Bit 16Mx32 1.8V 90-Pin VFBGA |
| W949D2CBJX5I TR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ, INDUST |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。