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參數(shù)資料
| 型號： | W948D6FBHX6G |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 5 ns, PBGA60 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60 |
| 文件頁數(shù)： | 56/60頁 |
| 文件大?。?/td> | 1147K |
| 代理商： | W948D6FBHX6G |
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W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 6 -
Revision A01-003
4. PIN DESCRIPTION
4.1 Signal Descriptions
SIGNAL NAME
TYPE
FUNCTION
DESCRIPTION
A [ n : 0 ]
Input
Address
Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the opcode
during a MODE REGISTER SET command.
A10 is used for Auto Pre-charge Select.
BA0, BA1
Input
Bank Select
Define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
I/O
Data Input/
Output
Data bus: Input / Output.
CS
Input
Chip Select
CS enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when
CS is
registered HIGH.
CS provides for external bank selection on
systems with multiple banks.
CS is considered part of the
command code.
RAS
Input
Row Address
Strobe
RAS , CAS and WE (along with CS ) define the command
being entered.
CAS
Input
Column Address
Strobe
Referred to
RAS
WE
Input
Write Enable
Referred to
RAS
UDM / LDM(x16);
DM0 to DM3 (x32)
Input
Input Mask
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading matches
the DQ and DQS loading.
x16: LDM: DQ0 - DQ7, UDM: DQ8
– DQ15
x32: DM0: DQ0 - DQ7, DM1: DQ8
– DQ15,
DM2: DQ16
– DQ23, DM3: DQ24 – DQ31
CK / CK
Input
Clock Inputs
CK and
CK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of
CK and negative edge of CK .Input and output data is
referenced to the crossing of CK and CK (both directions of
crossing). Internal clock signals are derived from CK/
CK .
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W949D2CB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512Mb Mobile LPDDR |
| W949D2CBJX5E | 功能描述:IC LPDDR SDRAM 512MBIT 90VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| W949D2CBJX5ETR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ |
| W949D2CBJX5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip Mobile LPDDR SDRAM 512M-Bit 16Mx32 1.8V 90-Pin VFBGA |
| W949D2CBJX5I TR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ, INDUST |
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