參數(shù)資料
型號: W948D6FBHX6G
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 8M X 16 DDR DRAM, 5 ns, PBGA60
封裝: 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-60
文件頁數(shù): 28/60頁
文件大?。?/td> 1147K
代理商: W948D6FBHX6G
W948D6FB / W948D2FB
256Mb Mobile LPDDR
Publication Release Date : May, 24, 2011
- 34 -
Revision A01-003
7.6.1 Write Command
= Don't Care
(High)
CK
CKE
CS
RAS
CAS
WE
A0-An
CA
AP
BA=BANK Address
CA=Coulmn Address
AP=Auto Precharge
BA
BA0,BA1
A10
Enable AP
Disable AP
7.6.2 Basic Write Timing Parameters
Basic Write timing parameters for DQs are shown in figure below; they apply to all Write operations.
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory;
if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to
that byte / column location.
DI
n
DI
n
tCK
tCH
tCL
tDSH
tDQSH
tDQSS
tWPRES
tWPRE
tDS
tDH
tDQSL
tWPST
CK
DQS
DQ, DM
Case 1:
tDQSS =
min
Case 2:
tDQSS =
max
tDH
tDS
tWPRES
tWPRE
tDQSH
tDQSS
tDSS
tDQSL
tDSS
tWPST
= Don't Care
1) DI n=Data In for column n
2) 3 subsequent elements of Data In are applied in the programmed order following DI n.
3) tDQSS: each rising edge of DQS must fall within the +/-25% window of the corresponding positive
clock edge.
DQ, DM
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