
CHAPTER 3 CPU FUNCTION
Preliminary User’s Manual U16541EJ1V0UM
96
3.4.7
Peripheral I/O registers
(1/11)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
18
16
Default Value
FFFFF004H
Port DL
PDL
√
Undefined
FFFFF004H
Port DLL
PDLL
√√
Undefined
FFFFF005H
Port DLH
PDLH
√√
Undefined
FFFFF006H
Port DH
PDH
√√
Undefined
FFFFF00AH
Port CT
PCT
√√
Undefined
FFFFF00CH
Port CM
PCM
√√
Undefined
FFFFF024H
Port mode register DL
PMDL
√
FFFFH
FFFFF024H
Port mode register DLL
PMDLL
√√
FFH
FFFFF025H
Port mode register DLH
PMDLH
√√
FFH
FFFFF026H
Port mode register DH
PMDH
√√
FFH
FFFFF02AH
Port mode register CT
PMCT
√√
FFH
FFFFF02CH
Port mode register CM
PMCM
√√
FFH
FFFFF044H
Port mode control register DL
PMCDL
√
0000H
FFFFF044H
Port mode control register DLL
PMCDLL
√√
00H
FFFFF045H
Port mode control register DLH
PMCDLH
√√
00H
FFFFF046H
Port mode control register DH
PMCDH
√√
00H
FFFFF04AH
Port mode control register CT
PMCCT
√√
00H
FFFFF04CH
Port mode control register CM
PMCCM
√√
00H
FFFFF064H
Peripheral I/O area select control register
BPC
Note
√
0000H
FFFFF066H
Bus size configuration register
BSC
√
5555H
FFFFF06EH
System wait control register
VSWC
√
77H
FFFFF080H
DMA source address register 0L
DSA0L
√
Undefined
FFFFF082H
DMA source address register 0H
DSA0H
√
Undefined
FFFFF084H
DMA destination address register 0L
DDA0L
√
Undefined
FFFFF086H
DMA destination address register 0H
DDA0H
√
Undefined
FFFFF088H
DMA source address register 1L
DSA1L
√
Undefined
FFFFF08AH
DMA source address register 1H
DSA1H
√
Undefined
FFFFF08CH
DMA destination address register 1L
DDA1L
√
Undefined
FFFFF08EH
DMA destination address register 1H
DDA1H
√
Undefined
FFFFF090H
DMA source address register 2L
DSA2L
√
Undefined
FFFFF092H
DMA source address register 2H
DSA2H
√
Undefined
FFFFF094H
DMA destination address register 2L
DDA2L
√
Undefined
FFFFF096H
DMA destination address register 2H
DDA2H
√
Undefined
FFFFF098H
DMA source address register 3L
DSA3L
√
Undefined
FFFFF09AH
DMA source address register 3H
DSA3H
√
Undefined
FFFFF09CH
DMA destination address register 3L
DDA3L
√
Undefined
FFFFF09EH
DMA destination address register 3H
DDA3H
√
Undefined
FFFFF0C0H
DMA transfer count register 0
DBC0
√
Undefined
FFFFF0C2H
DMA transfer count register 1
DBC1
√
Undefined
FFFFF0C4H
DMA transfer count register 2
DBC2
√
Undefined
FFFFF0C6H
DMA transfer count register 3
DBC3
R/W
√
Undefined
Note CAN controller version only