
CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual U16541EJ1V0UM
56
2.3
Description of Pin Functions
(1) P02 to P05 (Port 0) … 3-state I/O
P02 to P05 function as a 5-bit I/O port for which input and output can be specified in 1-bit units.
In addition to I/O port pins, these pins can also be used as an NMI input, external interrupt request signal
inputs, the external trigger for the A/D converter, and debug reset input. The port or control mode can be
selected for each bit, and a pin’s valid edge is specified by the INTR0 and INTF0 registers.
Normal output and N-ch open-drain output can be selected for P02 to P05.
(a) Port mode
P02 to P05 can be set to input or output in 1-bit units using port mode register 0 (PM0).
(b) Control mode
(i)
NMI (non-maskable interrupt request) … Input
This is a non-maskable interrupt request signal input pin.
(ii)
INTP0 to INTP3 (interrupt request from peripherals) … Input
These are external interrupt request signal input pins.
(iii) ADTRG (A/D trigger input) … Input
This is the A/D converter’s external trigger input pin. This pin is controlled by A/D converter mode
register 0 (ADA0M0).
(iv) DRST (debug reset) … Input
This is the debug reset input pin. This is a negative logic signal that initializes the on-chip debug
circuit asynchronously. When set to low level, it resets/disables the on-chip debug circuit. When not
using the debug function, set this pin to low level (DRST is valid only in the flash memory version).
(2) P10, P11 (Port 1) … 3-state I/O
P10 and P11 function as a 2-bit I/O port for which input and output can be specified in 1-bit units.
In addition to I/O pins, these pins can also be used as the analog output pins for the A/D converter in the
control mode. When using these pins as analog output pins, set them in the input mode. At this time, do not
read the port.
(a) Port mode
P10 and P11 can be set to input or output in 1-bit units using port mode register 1 (PM1).
(b) Control mode
(i)
ANO0, ANO1 (analog output) … Output
These are analog output pins for the D/A converter.