
Preliminary User’s Manual U16541EJ1V0UM
31
LIST OF TABLES (4/4)
Table No.
Title
Page
22-1
Interrupt Source List ...................................................................................................................................... 739
22-2
NMI Valid Edge Specification ........................................................................................................................ 747
22-3
Interrupt Control Register (xxICn) ................................................................................................................. 756
22-4
Valid Edge Specification ............................................................................................................................... 762
22-5
Valid Edge Specification ............................................................................................................................... 763
22-6
Valid Edge Specification ............................................................................................................................... 764
23-1
Assignment of Key Return Detection Pins .................................................................................................... 775
24-1
Standby Modes ............................................................................................................................................. 777
24-2
Operation After Releasing HALT Mode by Interrupt Request Signal ............................................................ 780
24-3
Operation Status in HALT Mode ................................................................................................................... 781
24-4
Operation After Releasing IDLE1 Mode by Interrupt Request Signal ........................................................... 783
24-5
Operation Status in IDLE1 Mode................................................................................................................... 783
24-6
Operation After Releasing IDLE2 Mode by Interrupt Request Signal ........................................................... 785
24-7
Operation Status in IDLE2 Mode................................................................................................................... 785
24-8
Operation After Releasing Software STOP Mode by Interrupt Request Signal............................................. 788
24-9
Operation Status in Software STOP Mode.................................................................................................... 788
24-10
Operation Status in Subclock Operation Mode ............................................................................................. 791
24-11
Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal ...................................................... 793
24-12
Operation Status in Sub-IDLE Mode ............................................................................................................. 793
25-1
Hardware Status on RESET Pin Input .......................................................................................................... 796
25-2
Hardware Statuses During WST2RES Signal Generation ............................................................................ 798
25-3
Hardware Statuses During Reset Operation by Low-Voltage Detector......................................................... 800
25-4
Operation Status of Clock Monitor (CLM.CLME Bit = 1, with Ring-OSC Operating) ..................................... 804
27-1
Correspondence Between CORCN Register Bits and CORADn Registers .................................................. 811
28-1
Signal Generation of Dedicated Flash Programmer (PG-FP4) ..................................................................... 818
28-2
Relationship of Operation Mode of FLMD0 and FLMD1 Pins ....................................................................... 820
28-3
Pins Used by Serial Interfaces ...................................................................................................................... 821
28-4
List of Communication Modes ....................................................................................................................... 826
28-5
Flash Memory Control Command.................................................................................................................. 827
28-6
Response Commands................................................................................................................................... 827