
CHAPTER 22 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Preliminary User’s Manual U16541EJ1V0UM
741
Table 22-1. Interrupt Source List (3/3)
Type
Classification
Default
Priority
Name
Trigger
Generating
Unit
Exception
Code
Handler
Address
Restored
PC
Interrupt
Control
Register
43
INTUA1R/
INTIIC2
Note 1
UARTA1 reception completion/
UARTA1 reception error/
IIC2 transfer completion
UARTA1/
IIC2
0330H
00000330H
nextPC
UA1RIC/
IICIC2
44
INTUA1T
UARTA1 transmission enable
UARTA1
0340H
00000340H
nextPC
UA1TIC
45
INTUA2R/
INTIIC0
Note 1
UARTA2 reception completion/
IIC0 transfer completion
UARTA/
IIC0
0350H
00000350H
nextPC
UA2RIC/
IICIC0
46
INTUA2T
UARTA2 transmission enable
UARTA2
0360H
00000360H
nextPC
UA2TIC
47
INTAD
A/D conversion completion
A/D
0370H
00000370H
nextPC
ADIC
48
INTDMA0
DMA0 transfer completion
DMA
0380H
00000380H
nextPC
DMAIC0
49
INTDMA1
DMA1 transfer completion
DMA
0390H
00000390H
nextPC
DMAIC1
50
INTDMA2
DMA2 transfer completion
DMA
03A0H
000003A0H
nextPC
DMAIC2
51
INTDMA3
DMA3 transfer completion
DMA
03B0H
000003B0H
nextPC
DMAIC3
52
INTKR
Key return interrupt
KR
03C0H
000003C0H
nextPC
KRIC
53
INTWTI
Watch timer interval
WT
03D0H
000003D0H
nextPC
WTIIC
54
INTWT
Watch timer reference time
WT
03E0H
000003E0H
nextPC
WTIC
55
INTC0ERR
Note 2/
INTERR
Note 3
AFCAN0 error/IEBus error
AFCAN0/
IEBus
03F0H
000003F0H
nextPC
ERRIC0/
ERRIC
56
INTC0WUP
Note 2/
INTSTA
Note 3
AFCAN0 wakeup/
IEBus status
AFCAN0/
IEBus
0400H
00000400H
nextPC
WUPIC0/
STSAIC
57
INTC0REC
Note 2/
INTIE1
Note 3
AFCAN0 reception/
IEBus data interrupt
AFCAN0/
IEBus
0410H
00000410H
nextPC
RECIC0/
IEIC1
Maskable
Interrupt
58
INTC0TRX
Note 2/
INTIE2
Note 3
AFCAN0 transmission/
IEBus error/IEBus status
AFCAN0/
IEBus
0420H
00000420H
nextPC
TRXIC0/
IEIC2
Notes 1. I
2C bus version (Y version) only
2. CAN controller version only
3. IEBus controller version only
Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the same
time. The highest priority is 0.
Restored PC:
The value of the program counter (PC) saved to EIPC or FEPC when interrupt
servicing is started. Note, however, that the restored PC when a non-maskable or
maskable interrupt is acknowledged while one of the following instructions is being
executed does not become the nextPC (if an interrupt is acknowledged during
interrupt execution, execution stops, and then resumes after the interrupt servicing
has finished).
Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W)
Division instructions (DIV, DIVH, DIVU, DIVHU)
PREPARE, DISPOSE instructions (only if an interrupt is generated before the
stack pointer is updated)
nextPC:
The PC value that starts the processing following interrupt/exception processing.
2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated
by (Restored PC
4).