
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Preliminary User’s Manual U16541EJ1V0UM
391
UAnTSF
When the UAnPWR bit of the UAnCTL0 register = 0 or the UAnTXE bit
of the UAnCTL0 register = 0 has been set.
When, following transfer completion, there was no next data transfer
from UAnTX
Write to UAnTXB bit
UAnTSF
0
1
Transfer status flag
UAnSTR
(n = 0 to 2)
0
UAnPE
UAnFE
UAnOVE
6
5
4
3
<2>
<1>
After reset: 00H
R/W
Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H,
UA2STR FFFFFA24H
The UAnTSF bit is always 1 when performing continuous transmission. When
initializing the transmission unit, check that the UAnTSF bit = 0 before performing
initialization. The transmit data is not guaranteed when initialization is performed
while the UAnTSF bit = 1.
When the UAnPWR bit of the UAnCTL0 register = 0 or the UAnRXE bit
of the UAnCTL0 register = 0 has been set.
When 0 has been written
UAnPE
0
1
Parity error flag
The operation of the UAnPE bit is controlled by the settings of the UAnPS1 and
UAnPS0 bits of the UAnCTL0 register.
The UAnPE bit can be read and written, but it can only be cleared by writing 0 to it, and
it cannot be set by writing 1 to it. When 1 is written to this bit, the hold status is entered.
When the UAnPWR bit of the UAnCTL0 register = 0 or the UAnRXE bit
of the UAnCTL0 register = 0 has been set
When 0 has been written
When no stop bit is detected during reception
UAnFE
0
1
Framing error flag
Only the first bit of the receive data stop bits is checked, regardless of the value
of the UAnSL bit of the UAnCTL0 register.
The UAnFE bit can be both read and written, but it can only be cleared by
writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit, the
hold status is entered.
When the UAnPWR bit of the UAnCTL0 register = 0 or the UAnRXE bit
of the UAnCTL0 register = 0 has been set.
When 0 has been written
When receive data has been set to the UAnRXB register and the next
receive operation is completed before that receive data has been read
UAnOVE
0
1
Overrun error flag
When an overrun error occurs, the data is discarded without the next receive data
being written to the receive buffer.
The UAnOVE bit can be both read and written, but it can only be cleared by writing
0 to it. When 1 is written to this bit, the hold status is entered.
<7>
<0>