
CHAPTER 18 IEBus CONTROLLER
Preliminary User’s Manual U16541EJ1V0UM
540
(a) Slave request flag (SLVRQ)...Bit 6
A flag indicating whether there has been a slave request from the master.
<Set/clear conditions>
Set:
When the unit is requested as a slave (if the condition in Table 18-13 Slave Request Condition
(SLVRQ Bit Setting Condition) is satisfied), this flag is set (1) by hardware when the
acknowledge period of the slave address field starts.
Clear: This flag is cleared (0) by hardware when the unit is not requested as a slave (if the condition in
Table 18-13 Slave Request Condition (SLVRQ Bit Setting Condition) is not satisfied). The
reset timing is the same as the set timing. If the unit is requested as a slave immediately after
communication has been correctly received (when the SLVRQ bit = 1), and if a parity error occurs
in the slave address field for that communication, the flag is not cleared.
Table 18-13. Slave Request Condition (SLVRQ Bit Setting Condition)
Status of Unit
Received Master
Address
Communication Mode
Received Slave Address
Individual
UAR register matching
Group matching
Not locked
don’t care
Broadcast
FFFH
Individual
UAR register matching
Group matching
Locked
Locked master matching
Broadcast
FFFH
Caution
If a unit other than the locked master communicates with the unit while the unit is
locked, the SLVRQ bit is not set but the ACK signal is returned to the slave address field.
This is because communication must be continued, even if a unit other than the locked
master returns the signal, if the control data is a slave status request.
(b) Arbitration result flag (ARBIT)...Bit 5
A flag that indicates the result of arbitration.
<Set/clear conditions>
Set:
This flag is set (1) when the data output by the IEBus unit during the arbitration period does not
match the bus line data.
Clear: This flag is cleared (0) by the start bit timing.
Cautions 1. The timing at which the arbitration result flag (ARBIT bit) is cleared differs depending
on whether the unit outputs a start bit.
If start bit is output: The flag is cleared at the output start timing.
If start bit is not output: The flag is cleared at the detection timing of the start bit
(approx. 160
s (mode 1, at 6.29 MHz) after output)
2. The flag is cleared (0) at the detection timing of the start bit if the other unit outputs
the start bit earlier and the unit does not output the start bit after the master request.