
1–1
1 Overview
1.1
Description
The TSB12LV01A is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed
serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01A
provides a high-performance IEEE 1394-1995 interface with the capability of transferring data between the
32-bit host bus, the 1394 PHY-link interface, and external devices connected to the local bus interface. The
1394 PHY-link interface provides the connection to the 1394 physical (PHY) layer device and is supported
by the link-layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet
data between the FIFO and PHY-link interface at rates of 100Mbit/s, 200Mbit/s, and 400Mbit/s. The
TSB12LV01A transmits and receives correctly-formatted 1394 packets and generates and inspects the
32-bit cyclic redundancy check (CRC). The TSB12LV01A is capable of being cycle master and supports
reception of isochronous data on two channels or all isochronous channels. TSB12LV01A has a generic
32-bit host bus interface, which connects to most 32-bit hosts. The LLC also provides the capability to
receive status from the physical layer device and to access the physical layer control and status registers
by the application software. An internal 2K-byte memory can be configured as multiple variable-size FIFOs
and eliminates the need for external FIFOs. Separate FIFOs can be user-configured to support general 1394
receive, asynchronous transmit, and isochronous transmit transfer operations. These functions are
accomplished by appropriately sizing the general receive FIFO (GRF), asynchronous transmit FIFO (ATF),
and isochronous transmit FIFO (ITF).
The TSB12LV01A provides bus holding buffers on the PHY interface for simple and cost effective
single-capacitor isolation.
The TSB12LV01A is a revision of the TSB12C01A, with feature enhancements and corrections. All errata
items to the TSB12C01A have been corrected, and the following feature enhancements have been made:
Cycle start packets can be stored in the GRF.
Isochronous and asynchronous packet transmit and receive can be enabled/disabled
independently. Asynchronous transmit is disabled upon reset, while isochronous transmit and
receive is unaffected.
One, two, or all isochronous channels can be received.
When receiving packets, RxDta can be programmed to interrupt the host processor on
programmable block boundaries, so the host can retrieve data from the GRF when each block
is available.
This is especially useful if the GRF is smaller than the expected receive packet size. RxDta can
also be programmed to interrupt the host processor when each packet is received.
Host bus burst mode data transfer is supported, at the peak rate of one quadlet (four bytes) per
BClk cycle for ATF write, ITF write, and GRF read.
A FIFO status read can be accomplished in three BClk cycles: 1. Address cycle 2. Data cycle
3. Idle cycle
Several changes in the register map have been made to improve host bus data throughput and
reduce status read and interrupt overhead. ATF status (30h), ITF status (34h) and GRF status
(3Ch) contains only status information. FIFO control (1Ch) is defined to control ATF size, ITF size,
clear FIFO function, and block size for GRF received packet. ATF status register and ITF status
register will report flags: full, empty and available space for host bus burst write. GRF status
register will report flags: empty, total stored data count, and next received block size.