參數(shù)資料
型號： TSB12LV01APZ
廠商： Texas Instruments, Inc.
英文描述： High-Speed Serial-Bus Link-Layer Controller
中文描述： 高速串行總線鏈路層控制器
文件頁數(shù)： 36/71頁
文件大?。?/td> 267K
代理商： TSB12LV01APZ
3–18
{0, quadlet_4[0:31]}
{0, quadlet_5[0:31]}
{0, quadlet_6[0:31]}
{1, 0004_0670} <– second packet token, PacComp = 0
{0, quadlet_7[0:31]}
{0, quadlet_8[0:31]}
{0, quadlet_9[0:31]}
{0, quadlet_10[0:31]}
{0, quadlet_11[0:31]}
{0, quadlet_12[0:31]}
{1, 0014_0271} <– the last packet token, PacComp = 1, Ack = 4’0001
{0, quadlet_13[0:31]}
{0, quadlet_14[0:31]}
This following example generates one RxDta interrupt. If the trigger size function is disabled, the data is
stored in the GRF as follows:
{1, 0014_0E71} <– packet token, PacComp = 1, WriteCount = 14, Ack = 4’0001
{0, quadlet_1[0:31]}
{0, quadlet_2[0:31]}
{0, quadlet_3[0:31]}
{0, quadlet_4[0:31]}
{0, quadlet_5[0:31]}
{0, quadlet_6[0:31]}
{0, quadlet_7[0:31]}
{0, quadlet_8[0:31]}
{0, quadlet_9[0:31]}
{0, quadlet_10[0:31]}
{0, quadlet_11[0:31]}
{0, quadlet_12[0:31]}
{0, quadlet_13[0:31]}
{0, quadlet_14[0:31]}
3.3.5
The purpose of RAM test mode is to test the RAM with writes and reads. During RAM test mode, RAM, which
makes up the ATF, ITF, and GRF, is accessed directly from the host bus. Different data is written to and read
back from the RAM and compared with what was expected to be read back. ATF status, ITF status, and GRF
status are not changed during RAM test mode, but the stored data in RAM is changed by any write
transaction. To enable RAM test mode, set RAMTest bit of the ATF Status register. Before beginning any
read or write to the RAM, the Adr_clr bit of the ATF Status register should be set to clear ConErr. This action
also clears the Adr_clr bit.
RAM Test Mode
During RAM test mode, the host bus address should be C0h. The first host bus transaction (either read or
write) accesses location 0 of the RAM. The second host bus transaction accesses location 1 of the RAM.
The nth host bus transaction accesses location n–1 of the RAM. After each transaction, the internal RAM
address counter is incremented by one.
The RAM has 512 locations with each location containing 33 bits. The most significant bit is the control bit.
When the control bit is set, that indicates the quadlet is the start of the packet. In order to set the control bit,
control bit of the ATF status register has to be set. In order to clear the control bit, control bit of the ATF status
register has to be cleared. When a write occurs, the 32 bits of data from the host bus is written to the low
order 32 bits of the RAM and the value in control-bit1 is written to the control bit. When a read occurs, the
low order 32 bits of RAM are sent to the host data bus and the control bit is compared to the control bit of
the ATF Status register. If the control bit and control bit of the ATF status register, ConErr of ATF status
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB12LV01B 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER
TSB12LV01B-EP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App.
TSB12LV01BIPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BIPZTEP 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER
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