參數(shù)資料
型號(hào): TSB12LV01APZ
廠商: Texas Instruments, Inc.
英文描述: High-Speed Serial-Bus Link-Layer Controller
中文描述: 高速串行總線鏈路層控制器
文件頁數(shù): 24/71頁
文件大?。?/td> 267K
代理商: TSB12LV01APZ
3–6
3.2.4
The interrupt and interrupt-mask registers work in tandem to inform the host bus interface when the state
of the TSB12LV01A changes. The interrupt register is at address 0Ch. The interrupt mask register is at
address 10h. The interrupt mask register is read/write. Its initial value is 0000_0000h. When regRW is
cleared to 0, the interrupt register (except for the Int bit) is cleared. When regRW (in diagnostics register
@20h) is set to 1, the interrupt register (including the Int bit) is read/write. Its initial value is 1000_0000h.
Interrupt and Interrupt-Mask Registers (@0Ch, @10h)
The interrupt bits all work the same. For example, when a phy interrupt occurs, the PhInt bit is set. If the
PhIntMask bit is set, the Int bit is set. If the IntMask is set, the INT signal is asserted. The logic for the interrupt
bits is shown in Figure 3–2. Table 3–4 defines the interrupt and interrupt-mask register field descriptions.
As shown in Figure 3–2, the INT bit is the OR of interrupt bits 1 – 31. When all the interrupt bits are cleared,
INT equals 0. When any of the interrupt bits are set, INT is set to 1, even if the INT bit was just cleared.
Set
Clear
Clk
PhInt Bit
Interrupt Bit (INT)
Other
Interrupts
Interrupt Bit
IntMask Bit
PhInt Bit
PhIntMask Bit
INT
DATA (01)
CS
WR
PhInt Source
SCLK
Q
Figure 3–2. Interrupt Logic Diagram Example
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