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參數(shù)資料
| 型號： | TSB12LV01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數(shù)： | 65/71頁 |
| 文件大?。?/td> | 267K |
| 代理商： | TSB12LV01APZ |
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7–5
7.6.1
The definition of the bits in the status transfer is shown in Table 7–9.
Table 7–9. Status-Request Functions (Length of Stream: 16 Bits)
Status Request
BIT(s)
NAME
DESCRIPTION
0
Arbitration reset
gap
The arbitration-reset gap bit indicates that the phy interface has detected that the bus
has been idle for an arbitration reset gap time (this time is defined in the IEEE 1394-1995
standard). This bit is used by the TSB12LV01A in its busy/retry state machine.
1
Fair gap
The fair-gap bit indicates that the phy interface has detected that the bus has been
idle for a fair-gap time (this time is defined in the IEEE 1394-1995 standard). This bit
is used by the TSB12LV01A to detect the completion of an isochronous cycle.
2
Bus reset
The bus reset bit indicates that the phy interface has entered the bus reset state.
3
phy interrupt
The phy interrupt bit indicates that the phy interface is requesting an interrupt to the
host.
4–7
Address
The address bits hold the address of the phy register whose contents are transferred
to the TSB12LV01A.
8–15
Data
The data bits hold the data that is to be sent to the TSB12LV01A.
Normally, the phy interface sends only the first four bits of data to the TSB12LV01A. These bits are used
by the TSB12LV01A state machine. However, if the TSB12LV01A initiates a read request (through a request
transfer), then the phy interface sends the entire status packet to the TSB12LV01A. Additionally, the phy
interface sends the contents of the register to the TSB12LV01A when it has some important information to
pass on. Currently, the only condition where this occurs is after the self–identification process when the phy
interface needs to inform the TSB12LV01A of its new node address (physical ID register).
There may be times when the phy interface wants to start a second status transfer. The phy interface first
has to wait at least one clock cycle with the CTL lines idle before it can begin a second transfer.
7.6.2
Transmit
When the TSB12LV01A wants to transmit information, it first requests access to the bus through an LREQ
signal. Once the phy interface receives this request, it arbitrates to gain control of the bus. When the phy
interface wins ownership of the serial bus, it grants the bus to the TSB12LV01A by asserting the transmit
state on the CTL terminals for at least one SCLK cycle. The TSB12LV01A takes control of the bus by
asserting either hold or transmit on the CTL lines. Hold is used by the TSB12LV01A to keep control of the
bus when it needs some time to prepare the data for transmission. The phy interface keeps control of the
bus for the TSB12LV01A by asserting a data–on state on the bus. It is not necessary for the TSB12LV01A
to use hold when it is ready to transmit as soon as bus ownership is granted.
When the TSB12LV01A is prepared to send data, it asserts transmit on the CTL lines as well as sends the
first bits of the packet on the D0 – D7 lines (assuming 400 Mb/s). The transmit state is held on the CTL
terminals until the last bits of data have been sent. The TSB12LV01A then asserts idle on the CTL lines for
one clock cycle after which it releases control of the interface.
However, there are times when the TSB12LV01A needs to send another packet without releasing the bus.
For example, the TSB12LV01A may want to send consecutive isochronous packets or it may want to attach
a response to an acknowledgment. To do this, the TSB12LV01A asserts hold instead of idle when the first
packet of data has been completely transmitted. Hold, in this case, informs the phy interface that the
TSB12LV01A needs to send another packet without releasing control of the bus. The phy interface then
waits a set amount of time before asserting transmit. The TSB12LV01A can then proceed with the transmittal
of the second packet. After all data has been transmitted and the TSB12LV01A has asserted idle on the CTL
terminals, the phy interface asserts its own idle state on the CTL lines. When sending multiple packets in
this fashion, it is required that all data be transmitted at the same speed. This is required because the
transmission speed is set during arbitration, and, since the arbitration step is skipped, there is no way of
informing the network of a change in speed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER |
| TSB12LV01B-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App. |
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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