參數(shù)資料
型號(hào)： TSB12LV01APZ
廠商： Texas Instruments, Inc.
英文描述： High-Speed Serial-Bus Link-Layer Controller
中文描述： 高速串行總線鏈路層控制器
文件頁(yè)數(shù)： 23/71頁(yè)
文件大小： 267K
代理商： TSB12LV01APZ
3–5
Table 3–3. Control-Register Field Descriptions (Continued)
BITS
8
ACRONYM
FUNCTION NAME
DESCRIPTION
RxIEn
Receive
isochronous
enable
When RxIEn is cleared, the receiver does not receive isochronous
packets.
9
AckCEn
Ack complete
enable
When AckCEn is set, the 12LV01A sends the Ack_complete code to the
transmit node for receiving a non-broadcast write request packet if
GRF is not full and there is no error in the packet. When AckCEn is
cleared, TSB12LV01A sends an Ack_pending code for the above
condition.
10
RstTx
Reset transmitter
When RstTx is set, the entire transmitter resets synchronously. This bit
clears itself.
11
RstRx
Reset receiver
When RstRx is set, the entire receiver resets synchronously. This bit
clears itself.
12–19
Reserved
Reserved
Reserved
20
CyMas
Cycle master
When CyMas is set and the TSB12LV01A is attached to the root phy,
the cyclemaster function is enabled. When the cycle_count field of the
cycle timer register increments, the transmitter sends a cycle-start
packet. This bit is not cleared upon bus reset. When another node is
selected as root during a bus reset, the transaction layer in the now
nonroot TSB12LV01A node must clear this bit and the transaction layer
in the TSB12LV01A node selected as root must set this bit.
21
CySrc
Cycle source
When CySrc is set, the cycle_count field increments and the
cycle_offset field resets for each positive transition of CYCLEIN. When
CySrc is cleared, the cycle_count field increments when the
cycle_offset field rolls over.
22
CyTEn
Cycle-timer enable
When CyTEn is set, the cycle_offset field increments. This bit must be
set to transmit cycle start packets for cycle master node. This bit
must
be set to receive or transmit isochronous packets.
23
TrgEn
Trigger size func-
tion enable
If TrgEn is set, the receiver partitions the received packet into trigger
size blocks. Trigger size is defined in FIFO Control register. For exam-
ple: if trigger size=8 and total received packet size (excluding header
CRC and data CRC)=20 quadlets. The receiver creates 3 blocks of
data in GRF. Each block starts with a packet token quadlet to indicate
how many quadlets follow this packet token. The first and the second
block have 9 quadlets (including the packet token quadlet). The third
block has 5 quadlets(including a packet token quadlet). Each block trig-
gers one RxDta interrupt. The purpose of the trigger size function is to
allow the receiver to receive a packet larger than GRF size and host bus
can read the received data when each block is available without waiting
till the whole packet is loaded into GRF, so the host bus latency is re-
duced.
24
IRP1En
IR port 1 enable
When IRP1En is set, the receiver accepts isochronous packets when
the channel number matches the value in the IR Port1 field.
25
IRP2En
IR port 2 enable
When IRP2En is set, the receiver accepts isochronous packets when
the channel number matches the value in the IR Port2 field.
26–30
31
Reserved
Reserved
Reserved
FhBad
Flush bad packets
When the FhBad is set, the receiver flushes any received bad packets
(including a partial packet due to GRF full)and it does not generate a
RxDta interrupt. When FhBad is set, it disables the TrgEn function.
This bit or bits are new to the TSB12LV01A and do not exist in the TSB12C01A.
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