參數(shù)資料
型號: TSB12LV01APZ
廠商: Texas Instruments, Inc.
英文描述: High-Speed Serial-Bus Link-Layer Controller
中文描述: 高速串行總線鏈路層控制器
文件頁數(shù): 19/71頁
文件大?。?/td> 267K
代理商: TSB12LV01APZ
3–1
3 Internal Registers
3.1
General
The host-bus processor directs the operation of the TSB12LV01A through a set of registers internal to the
TSB12LV01A itself. These registers are read or written by asserting CS with the proper address on ADDR0
– ADDR7 and asserting or deasserting WR depending on whether a read or write is needed. Figure 3–1 lists
the register addresses; subsequent sections describe the function of the various registers.
3.2
The TSB12LV01A internal registers control the operation of the TSB12LV01A. The bit definitions of the
internal registers are shown in Figure 3–1 and are described in subsections 3.2.1 through 3.2.12.
Internal Register Definitions
There are three modes to access the internal TSB12LV01A registers; normal mode, quick mode, and burst
mode. The registers from address 00h to 2Ch are accessed using normal mode as shown in Figures 6–2
and 6–3.
The registers 30h, 34h, 3Ch, and C0h may be accessed using quick mode reads as shown in Figure 6–5.
The registers 30h and 80h through 9Ch may be accessed using quick mode writes as shown in Figure 6–4.
NOTE:
The protocols for normal mode and quick mode are exactly the same. The only
difference being that quick mode simply returns CA quicker.
The registers 84h, 8Ch, 94h, 9Ch, A0h, and B0h may be accessed using burst mode writes as shown in
Figure 6–6.
The register C0h may be accessed using burst mode reads as shown in Figure 6–7.
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