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參數(shù)資料
| 型號： | TSB12LV01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數(shù)： | 34/71頁 |
| 文件大?。?/td> | 267K |
| 代理商： | TSB12LV01APZ |
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3–16
Writing to 90h(ITF_First) writes DATA0–DATA31 into the ITF and sets the control bit to 1 to indicate the first
quadlet of the packet, but the data is not confirmed for transmission.
It is allowed to burst write to 94h(ITF_Continue), which allows multiple quadlets to load into ITF, but the data
is not confirmed for transmission. If bursting writes to ITF_Continue & Update do not keep up with data being
put on the 1394 bus, an ITF underflow error will occur.
Writing to 9Ch (ITF_Continue & Update), which allows multiple quadlets to load into ITF, the data is
confirmed for transmission.
Writing to address B0h (ITF burst write) writes the whole packet into ITF. The first quadlet written into ITF
has the control bit set to 1 to indicate this is the first quadlet of the packet. The termination of the burst write
on the host interface confirms the packet for transmission.
ITF access example:
Assume there are n quadlets need to write to ITF for transmission.
Example 3–6. Non-Burst Write
90h (ITF_First) DATA1[0:31]
94h (ITF_Continue) DATA2[0:31]
. .
. .
94h (ITF_Continue) DATA(n–1)[0:31]
9Ch (ITF_Continue & Update) DATAn[0:31]
Example 3–7. Allowable Burst Write
90h (ITF_First) DATA1[0:31]
94h (ITF_Continue) (burst write) DATA2[0:31], DATA3[0:31],
……
, DATA(n–1)[0:31]
9Ch (ITF_Continue & Update) DATAn[0:31]
Example 3–8. Allowable Burst Write, But Riskier
90h (ITF_First) DATA1[0:31]
9Ch (ITF_Continue & Update) (burst write) DATA2[0:31], DATA3[0:31],
…
., DATA(n–1)[0:31],
DATAn[0:31].
NOTE:
If consecutive writes to ITF_Continue & Update do not keep up with data being put
on the 1394 bus, an ITF underflow error will occur.
Example 3–9. Allowable Burst Write
B0h (ITF burst write) DATA1[0:31], DATA2[0:31],
…
., DATA(n–1)[0:31], DATAn[0:31]
Example 3–9 only requires one host bus write transaction. The packet stores in ITF as following
format:
{1, DATA1[0:31]}
{0, DATA2[0:31]}
{0, DATA3[0:31]}
.
.
{0, DATA(n–1)[0:31]}
{0, DATAn[0:31]}
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER |
| TSB12LV01B-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App. |
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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