參數(shù)資料
型號： TSB12LV01APZ
廠商： Texas Instruments, Inc.
英文描述： High-Speed Serial-Bus Link-Layer Controller
中文描述： 高速串行總線鏈路層控制器
文件頁數(shù)： 21/71頁
文件大?。?/td> 267K
代理商： TSB12LV01APZ
3–3
3.2.1
The version/revision register allows software to be written that supports multiple versions of the high-speed
serial-bus link-layer controllers. This register is at address 00h and is read only. The initial value is
3031_3042h.
Version/Revision Register (@00h)
Table 3–1. Version/Revision Register Field Descriptions
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
0–15
Version
Version
Version of the
TSB12LV01A
16–31
Revision
Revision
Revision of the
TSB12LV01A
3.2.2
The node-address/transmitter acknowledge register controls which packets are accepted/rejected, and it
presents the last acknowledge received for packets sent from the ATF. This register is at offset 04h. The
bus number and node number fields are read/write. The AT acknowledge (ATAck) received is normally read
only. Setting the regRW bit in the diagnostic register makes these fields read/write. The initial value is
FFFF_0000h. The node number field and the root field are automatically updated by every PHY register 0
status transfer to the TSB12LV01A.
Node-Address/Transmitter Acknowledge Register (@04h)
Table 3–2. Node-Address/Transmitter Acknowledge Register Field Descriptions
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
0–9
BusNumber
Bus number
BusNumber is the 10-bit IEEE 1212 bus number that the
TSB12LV01A uses with the node number in the SOURCE
address for outgoing packets and to accept or reject incoming
packets. The TSB12LV01A always accepts packets with a bus
number equal to 3FFh.
10–15
NodeNumber
Node number
NodeNumber is the 6-bit node number that the TSB12LV01A
uses with the bus number in the source address for outgoing
packets and to accept or reject incoming packets. The
TSB12LV01A always accepts packets with the node address
equal to 3Fh. After bus reset, the node number is automatically
set to the node’s Physical_ID by a PHY register 0 transfer.
16
Root
Root
If Root =1 this node is root, read only
17–22
23–27
Reserved
Reserved
Reserved
ATAck
Address transmitter
acknowledge
received
ATAck is the last acknowledge received by the transmitting
node in response to a packet sent from the asynchronous
transmit-FIFO.
ATAck=0_XXXX the low order 4 bits present normal ack code
receive from the receiving node.
ATAck=1_0000 an acknowledge timeout occured
ATAck=1_0011 ack packet error (ack parity error, or ack
pPending too long or ack pending too short)
28–30
This bit is new to the TSB12LV01A and does not exist in the TSB12C01A.
The bit number of these bits is different than the bit number listed for the TSB12C01A.
Reserved
Reserved
Reserved
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB12LV01B 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER
TSB12LV01B-EP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App.
TSB12LV01BIPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BIPZTEP 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER
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