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參數(shù)資料
| 型號： | TSB12LV01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數(shù)： | 28/71頁 |
| 文件大?。?/td> | 267K |
| 代理商： | TSB12LV01APZ |
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3–10
3.2.8
The diagnostic control and status register allows for the monitoring and control of the diagnostic features
of the TSB12LV01A. The register is at address 20h. The regRW and enable snoop bits are read/write. When
regRW is cleared, all other bits are read only. When regRW is set, all bits are read/write. Its initial value is
0000_0000h.
Diagnostic Control Register (@20h)
Table 3–8. Diagnostic Control and Status-Register Field Descriptions
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
0
ENSp
Enable snoop
When ENSp is set, the receiver accepts all packets on the bus
regardless of address or format. The receiver uses the snoop data
format defined in Section 4.4.
1–3
Reserved
Reserved
Reserved
4
regR/W
Register read/write
access
When regR/W is set, most registers are fully read/write.
5–31
This bit or bits are new to the TSB12LV01A and do not exist in the TSB12C01A.
Reserved
Reserved
Reserved
3.2.9
The phy-chip access register allows access to the registers in the attached phy chip. The most significant
16 bits send read and write requests to the phy-chip registers. The least significant 16 bits are for the phy
chip to respond to a read request sent by the TSB12LV01A. The phy-chip access register also allows the
phy interface to send important information back to the TSB12LV01A. When the phy interface sends new
information to the TSB12LV01A, the phy register-information-receive (PhyRRx) interrupt is set. The register
is at address 24h and is read/write. Its initial value is 0000_0000h. All gap counts (set in the phy device
registers) on all nodes of a 1394 bus must be identical. This can be accomplished by using the phy
configuration packets to set a specific gap count or by using two bus resets, which resets the gap counts
to the default 3Fh. See Section 4.6 for the format of the phy configuration packets.
Phy-Chip Access Register (@24h)
Table 3–9. Phy-Chip Access Register
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
0
RdPhy
Read phy-chip
register
When RdPhy is set, the TSB12LV01A sends a read register request
with address equal to phyRgAd to the phy interface. This bit is cleared
when the request is sent.
1
WrPhy
Write phy-chip
register
When WrPhy is set, the TSB12LV01A sends a write register request
with an address equal to phyRgAd on to the phy interface. This bit is
cleared when the request is sent.
2–3
Reserved
Reserved
Reserved
4–7
PhyRgAd
Phy-chip-register
address
PhyRgAd is the address of the phy-chip register that is to be accessed.
8–15
PhyRgData
Phy-chip-register
data
PhyRgData is the data to be written to the phy-chip register indicated
in PhyRgAd.
16–19
Reserved
Reserved
Reserved
20–23
PhyRxAd
Phy-chip-register-
received address
PhyRxAd is the address of the register from which PhyRxData came.
24–31
PhyRxData
Phy-chip-register-
received data
PhyRxData contains the data from register addressed by PhyRxAd.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER |
| TSB12LV01B-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App. |
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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