參數(shù)資料
型號: TSB12LV01APZ
廠商: Texas Instruments, Inc.
英文描述: High-Speed Serial-Bus Link-Layer Controller
中文描述: 高速串行總線鏈路層控制器
文件頁數(shù): 15/71頁
文件大小: 267K
代理商: TSB12LV01APZ
2–1
2 Architecture
2.1
Functional Block Diagram
The functional block architecture of the TSB12LV01A is shown in Figure 2–1.
Transmitter
Cycle Timer
Cycle Monitor
CRC
Receiver
Configuration Registers
GRF
ITF
ATF
P
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y
s
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f
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Figure 2–1. TSB12LV01A Block Diagram
2.1.1
Physical Interface
The physical (PHY) interface provides PHY-level services to the transmitter and receiver. This includes gain-
ing access to the serial bus, sending packets, receiving packets, sending and receiving acknowledge pack-
ets, and reading and writing PHY registers.
The PHY interface module also interfaces to the PHY chip and conforms to the PHY-link interface specifica-
tion described in Annex J of the IEEE 1394-1995 standard (refer to Section 7 of this document for more infor-
mation).
2.1.2
The transmitter retrieves data from either the ATF or the ITF and creates correctly formatted serial-bus
packets to be transmitted through the PHY interface. When data is present at the ATF interface to the
transmitter, the TSB12LV01A PHY interface requests the serial bus and upon receiving a grant, sends a
packet. When data is present at the ITF interface to the transmitter, the TSB12LV01A arbitrates for the serial
bus during the next isochronous cycle. The transmitter autonomously sends the cycle-start packets when
the chip is the cycle master. The PHY interface provides PHY-level services to the transmitter and receiver.
This includes gaining access to the serial bus, sending packets, receiving packets, and receiving status from
the physical layer.
Transmitter
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