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參數(shù)資料
| 型號： | TSB12LV01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數(shù)： | 64/71頁 |
| 文件大?。?/td> | 267K |
| 代理商： | TSB12LV01APZ |
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7–4
7.5.2
For fair or priority access, the TSB12LV01A requests control of the bus at least one clock after the
TSB12LV01A phy interface becomes idle. CTL0 – CTL1 = 00 indicates the physical layer is in an idle state.
If the TSB12LV01A senses that CTL0 – CTL1 = 10 (receive), then it knows that its request has been lost.
This is true any time during or after the TSB12LV01A sends the bus request transfer. Additionally, the phy
interface ignores any fair or priority requests when it asserts the receive state while the TSB12LV01A is
requesting the bus. The link then reissues the request one clock after the next interface idle.
Bus Request
The cycle master uses a priority request to send a cycle-start message. After receiving a cycle start, the
TSB12LV01A can issue an isochronous bus request. When arbitration is won, the TSB12LV01A proceeds
with the isochronous transfer of data. The isochronous request is cleared in the phy interface once the
TSB12LV01A sends another type of request or when the isochronous transfer has been completed.
The TakeBus request is issued when the TSB12LV01A needs to send an acknowledgment after reception
of an asynchronous packet addressed to it. This request must be issued during packet reception. This is
done to minimize the delay times that a phy interface would have to wait between the end of a packet
reception and the transmittal of an acknowledgment. As soon as the packet ends, the phy interface
immediately grants the bus access to the TSB12LV01A. The TSB12LV01A sends an acknowledgment to
the sender unless the header CRC of the packet turns out to be invalid. In this case, the TSB12LV01A
releases the bus immediately; it is not allowed to send another type of packet on this grant. To ensure this,
the TSB12LV01A is forced to wait160 ns after the end of the packet is received. The phy interface then gains
control of the bus. The bus is then released and allowed to proceed with another request.
Although highly improbable, it is conceivable that two separate nodes believe that an incoming packet is
intended for them. The nodes then issue a TakeBus request before checking the CRC of the packet. Since
both phys seize control of the bus at the same time, a temporary, localized collision of the bus occurs
somewhere between the competing nodes. This collision would be interpreted by the other nodes on the
network as being a ZZ line state, not a bus reset. As soon as the two nodes check the CRC, the mistaken
node drops its request and the false line state is removed. The only side effect is the loss of the intended
acknowledgment packet (this is handled by the higher layer protocol).
7.5.3
When the TSB12LV01A requests to read the specified register contents, the phy interface sends the
contents of the register to the TSB12LV01A through a status transfer. When an incoming packet is received
while the phy interface is transferring status information to the TSB12LV01A, the phy interface continues
to attempt to transfer the contents of the register until it is successful.
Read/Write Requests
For write requests, the phy interface loads the data field into the appropriately addressed register as soon
as the transfer has been completed. The TSB12LV01A is allowed to request read or write operations at any
time.
NOTE:
See Section 7.6, for a more detailed description of the status transfer.
Status
A status transfer is initiated by the phy interface when it has some status information to transfer to the
TSB12LV01A. The transfer is initiated by asserting the following: CTL0 – CTL1 = 01 and D0 – D1s used to
transmit the status data; see Table 7–9 for status-request functions. D2 – D7 are not used for status
transfers.
7.6
The status transfer can be interrupted by an incoming packet from another node. When this occurs, the phy
interface attempts to resend the status information after the packet has been acted upon. The phy interface
continues to attempt to complete the transfer until the information has been successfully transmitted.
NOTE:
There must be at least one idle cycle between consecutive status transfers.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER |
| TSB12LV01B-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App. |
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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