參數(shù)資料
型號(hào)： TSB12LV01APZ
廠商： Texas Instruments, Inc.
英文描述： High-Speed Serial-Bus Link-Layer Controller
中文描述： 高速串行總線鏈路層控制器
文件頁(yè)數(shù)： 27/71頁(yè)
文件大?。?/td> 267K
代理商： TSB12LV01APZ
3–9
3.2.6
The isochronous receive-port number register controls which isochronous channels are received by this
node. If RAI of Control register is set, this register value is don’t care since all channels are received. This
register is at address 18h. The register is read/write, and its initial value is 0000_0000h.
Isochronous Receive-Port Number Register (@18h)
Table 3–6. Isochronous Receive-Port Number Register Field Descriptions
BITS
0–1
ACRONYM
FUNCTION NAME
DESCRIPTION
TAG1
Tag bit 1
Isochronous data format tag. See IEEE 1394-1995 6.2.3 and
IEC 61883.
2–7
IRPort1
Isochronous receive
TAG bits and port 1
channel number
IRPort1 contains the channel number of the isochronous packets the
receiver accepts when IRP1En is set. See Table 4–5 and Table 4–6
for more information.
8–9
Tag2
Tag bit 2
Isochronous data format tag. See IEEE 1394-1995 6.2.3
10–15
IRPort2
Isochronous receive
TAG bits and port 2
channel number
IRPort2 contains the channel number of the isochronous packets the
receiver accepts when IRP2En is set (bits 8 and 9 are reserved as
TAG bits). See Table 4–5 and Table 4–6 for more information.
16–30
31
Reserved
Reserved
Reserved
Mon Tag
Tag enable
When set, it enables the tag bit comparison. If both Tagx and IR-
PORTx match for port number x, the matching receive Iso packet
is stored in the GRF.
This bit or bits are new to the TSB12LV01A and do not exist in the TSB12C01A.
FIFO Control Register (@1Ch)
FIFO Control register is used to clear ATF, ITF, GRF and set up the trigger size for the trigger-size function.
ATF size and ITF size are all in the quadlet. GRF size = 512–(ATF Size)– (ITF size)
3.2.7
Table 3–7. Node-Address/ Transmitter Acknowledge Register Field Descriptions
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
0
ClrATF
Clear asynchronous
transfer FIFO
Writing 1 to this bit automatically clears the ATF to 0. This bit is
self clearing.
1
ClrITF
Clear isochronous
transfer FIFO
Writing 1 to this bit automatically clears the ITF to 0. This bit is
self clearing.
2
ClrGRF
Clear general receive
FIFO
Writing 1 to this bit automatically clears the GRF to 0. This bit is
self clearing.
3–4
Reserved
Reserved
Reserved
5–13
Trigger Size
Trigger size
Trigger size is used to split a big receive packet into several
smaller blocks of data, so the host bus does not have to wait the
whole packet cycle before it can read the GRF, When TrgEn=0
or FhBad=1 in the control register, trigger size is don’t care. The
trigger size is specified in quadlets.
14–22
ATFSize
Asynchronous trans-
mitter FIFO size
ATFSize allocates ATF size in the quadlets. The limitations for
ATFSize are ATFSise<=512 and (ATFSize+ITFSize) <=512.
23–31
ITFSize
Isochronous trans-
mitter FIFO size
Same as above except for ITF
This register is new to the TSB12LV01A and does not exist in the TSB12C01A.
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參數(shù)描述
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