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參數(shù)資料
| 型號： | TSB12LV01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數(shù)： | 13/71頁 |
| 文件大?。?/td> | 267K |
| 代理商： | TSB12LV01APZ |
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1–5
Table 1–1. Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
PHY Interface
CTL1, CTL0
62, 63
I/O
Control 1 and control 0 of the PHY-link control bus. CTL1 and CTL0 indicate the four
operations that can occur in this interface (see Section 7 of this document or Annex
J of the IEEE 1394-1995 standard for more information about the four operations).
These terminals have bus holder functionality built in. When RESET is asserted,
CTL0 and CTL1 are initialized to 0 (low) for one SCLK cycle and then released. The
bus holders then hold CTL0 and CTL1 at 0 (low) until a transition is driven.
D0 – D7
52–55
57–60
I/O
Data 0 through data 7 of the PHY-link data bus. Data is expected on D0 – D1 for
100 Mbits/s packets, D0 – D3 for 200 Mbits/s, and D0 – D7 for 400 Mbits/s transfers.
These terminals have bus holder functionality built in. When RESET is asserted,
D0 – D7 are initialized to 0 (low) for one SCLK cycle and then released. The bus
holders then hold D0 – D7 at 0 (low) until a transition is driven.
ISO
69
I
Isolation barrier (active low). ISO is asserted (low) when an isolation barrier is
present. This terminal only supports bus holder type isolation.
LREQ
67
O
Link request. LREQ is a TSB12LV01A output that makes bus requests and access
requests to the PHY layer. On the first rising edge of SCLK when RESET is asserted,
LREQ is driven to 0 (low).
POWERON
76
O
Power on indicator to PHY interface. When active, POWERON has a clock output
with 1/16 of the BCLK frequency and indicates to the PHY interface that the
TSB12LV01A is powered. This terminal can be connected to the link power status
(LPS) terminal on the TI PHY devices to provide an indication of the LLC power
condition. When RESET is asserted, POWERON is driven to 0 (low).
SCLK
65
I
System clock. SCLK is a 49.152-MHz clock from the PHY, that generates the internal
24.576-MHz clock used internally in the TSB12LV01A.
Miscellaneous Signals
BCLK
32
I
Bus clock. BCLK is the host bus clock used for the host-interface module of the
TSB12LV01A. It is asynchronous to SCLK.
CYCLEIN
42
I
Cycle in. CYCLEIN is an optional external 8,000-Hz clock used to time the
isochronous cycle clock, and it should only be used when attached to the
cycle-master node. It is enabled by the cycle source bit and should be tied high when
not used.
CYCLEOUT
44
O
Cycle out. CYCLEOUT is the version of the isochronous cycle clock used by the
TSB12LV01A. It is based on the internal timer controls and received cycle-start
messages.
CYDNE
49
O
Status of CyDne bit. CYDNE indicates the value of the CyDne bit of the interrupt
register. This terminal is asserted for as long as the interrupt bit is assigned.
CYST
50
O
Status of CySt bit. CYST indicates the value of the CySt bit of the interrupt register.
This terminal is asserted for as long as the interrupt bit is set.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER |
| TSB12LV01B-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App. |
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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