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| 型號： | TSB12LV01APZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁數(shù)： | 25/71頁 |
| 文件大?。?/td> | 267K |
| 代理商： | TSB12LV01APZ |
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3–7
Table 3–4. Interrupt- and Mask-Register Field Descriptions
BITS
ACRONYM
FUNCTION NAME
DESCRIPTION
0
Int
Interrupt
Int contains the value of all interrupt and interrupt mask bits ORed
together.
1
PhInt
Phy chip interrupt
When PhInt is set, the phy chip has signaled an interrupt through the
pPhy interface.
2
PhyRRx
Phy register
information received
When PhyRRx is set, a register value has been transferred to the phy
chip access register (offset 24h) from the phy interface.
3
PhRst
Phy reset started
When PhRst is set, a phy-layer reconfiguration has started (1394 bus
reset).
4
SIDComp
Self ID complete
When SIDComp is set, a complete bus reset process is finished. If the
RxSId bit (bit 1) of the control register (08h) is set, the GRF contains
all received self-ID packets.
5
TxRdy
Transmitter ready
When TxRdy is set, the transmitter is idle and ready. When TxRdy is
set to 1 and AckV (bit 31 of node address register) remains 0 for a
non-broadcast asynchronous packet, the transmitter fails arbitration
and arbitrates for the bus again when the bus is idle.
6
RxDta
Receiver has data
In normal mode and when set, RxDta indicates that the receiver has
accepted a block of data(if TrgEn=0, a block of data means a packet)
into the GRF interface. However, during the self-ID portion of a bus
reset, this bit is set after the bus reset process is done.
7
CmdRst
Command reset
received
When CmdRst is set, the receiver has been sent a quadlet write
request addressed to the RESET_START CSR register.
8
ACKRCV
Receive ACK
Packet Interrupt
This interrupt is triggered when an acknowledge is received or a
timeout has occurred after an asynchronous packet is sent. To en-
able this register, the mask interrupt should be set to 1.
9–10
11
Reserved
Reserved
Reserved
ITBadF
Bad pPacket
formatted in ITF
When ITBadF is set, the transmitter has detected invalid data at the
isochronous transmit-FIFO interface.
12
ATBadF
Bad packet
formatted in ATF
When ATBadF is set, the transmitter has detected invalid data at the
asynchronous transmit-FIFO interface. If the first quadlet of a packet
is not written to the ATF_First or ATF_First & Update, the transmitter
enters a state denoted by an ATBadF interrupt. An underflow of the ATF
also causes an ATBadF interrupt. If this state is entered, no
asynchronous packets can be sent until the ATF is cleared by way of
the CLR ATF control bit. Isochronous packets can be sent while in this
state.
13
Reserved
Reserved
Reserved
14
SntRj
Busy acknowledge
sent by receiver
SntRj is set when there is a GRF overflow. The receiver is then forced
to send a busy acknowledge to a packet addressed to this node
because the GRF overflowed.
15
HdrEr
Header error
When HdrEr is set, the receiver detected a header CRC error on an
incoming packet that may have been addressed to this node. The
packet will be discarded.
16
TCErr
Transaction code
error
When TCErr is set, the transmitter detected an invalid transaction code
in the data at the transmit FIFO interface.
17–18
19
This bit is new to the TSB12LV01A and does not exist in the TSB12C01A.
Reserved
Reserved
Reserved
Isochronous cycle lasts more than 125
μ
s.
CyTmOut
Cycle timer out
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| TSB12LV01B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 HIGH SPEED SERIAL BUS LINK LAYER CONTROLLER |
| TSB12LV01B-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic High Performance 1394 3.3V Link Layer for Telecom. Embedded & Indust. App. |
| TSB12LV01BIPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BIPZTEP | 功能描述:1394 接口集成電路 Mil Enh Hi Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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