參數(shù)資料
型號: TSB12LV01APZ
廠商: Texas Instruments, Inc.
英文描述: High-Speed Serial-Bus Link-Layer Controller
中文描述: 高速串行總線鏈路層控制器
文件頁數(shù): 52/71頁
文件大?。?/td> 267K
代理商: TSB12LV01APZ
5–4
5.7
Phy-Interface Switching Characteristics Over Operating Free-Air
Temperature Range, C
L
= 45 pF (unless otherwise noted) (See Note 3)
PARAMETER
Delay time, SCLK
to D0 – D7 valid (see Figure 6–9)
Delay time, SCLK
to D0 – D7
↑↓
(see Figure 6–9)
Delay time, SCLK
to D0 – D7 invalid (see Figure 6–9)
Delay time, SCLK
to CTL0 – CTL1 valid (see Figure 6–9)
Delay time, SCLK
to CTL0 – CTL1
↑↓
(see Figure 6–9)
Delay time, SCLK
to CTL0 – CTL1 invalid (see Figure 6–9)
Delay time, SCLK
to LREQ
↑↓
(see Figure 6–11)
NOTE 3: These parameters are not production tested.
MIN
MAX
UNIT
td5
td6
td7
td8
td9
td10
td11
3
11
ns
3
11
ns
3
11
ns
3
11
ns
3
11
ns
3
11
ns
3
11
ns
5.8
Miscellaneous Timing Requirements Over Operating Free-Air
Temperature Range (see Figure 6–13 and Note 3)
PARAMETER
MIN
MAX
UNIT
μ
s
μ
s
μ
s
tc3
tw3(H)
tw3(L)
NOTE 3: These parameters are not production tested.
Cycle time, CYCLEIN (see Figure 6–13)
Pulse duration, CYCLEIN
(see Figure 6–13)
Pulse duration, CYCLEIN
(see Figure 6–13)
124.99
125.01
62
62
5.9
Miscellaneous Signal Switching Characteristics Over Operating Free-Air
Temperature Range (See Note 3)
PARAMETER
MIN
MAX
UNIT
td12
td13
td14
td15
NOTE 3: These parameters are not production tested.
Delay time, SCLK
to INT
(see Figure 6–12)
Delay time, SCLK
to INT
(see Figure 6–12)
Delay time, SCLK
to CYCLEOUT
(see Figure 6–14)
Delay time, SCLK
to CYCLEOUT
(see Figure 6–14)
4
18
ns
4
18
ns
4
16
ns
4
16
ns
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